static void ab8500_modify_reg_init(int id, u8 mask, u8 value)
{
int i;
if (machine_is_u8520()) {
for (i = ARRAY_SIZE(ab8505_reg_init) - 1; i >= 0; i--) {
if (ab8505_reg_init[i].id == id) {
u8 initval = ab8505_reg_init[i].value;
initval = (initval & ~mask) | (value & mask);
ab8505_reg_init[i].value = initval;
BUG_ON(mask & ~ab8505_reg_init[i].mask);
return;
}
}
} else {
for (i = ARRAY_SIZE(ab8500_reg_init) - 1; i >= 0; i--) {
if (ab8500_reg_init[i].id == id) {
u8 initval = ab8500_reg_init[i].value;
initval = (initval & ~mask) | (value & mask);
ab8500_reg_init[i].value = initval;
BUG_ON(mask & ~ab8500_reg_init[i].mask);
return;
}
}
}
BUG_ON(1);
}
void __init mop500_u8500uib_init(void)
{
int ret;
mop500_uib_i2c_add(3, mop500_i2c3_devices_u8500,
ARRAY_SIZE(mop500_i2c3_devices_u8500));
mop500_uib_i2c_add(0, mop500_i2c0_devices_u8500,
ARRAY_SIZE(mop500_i2c0_devices_u8500));
if (machine_is_hrefv60() || machine_is_u8520()) {
lsm303dlh_pdata_u8500.irq_a1 = HREFV60_ACCEL_INT1_GPIO;
lsm303dlh_pdata_u8500.irq_a2 = HREFV60_ACCEL_INT2_GPIO;
lsm303dlh_pdata_u8500.irq_m = HREFV60_MAGNET_DRDY_GPIO;
adp1653_pdata_u8500_uib.enable_gpio =
HREFV60_CAMERA_FLASH_ENABLE;
} else {
lsm303dlh_pdata_u8500.irq_a1 = GPIO_ACCEL_INT1;
lsm303dlh_pdata_u8500.irq_a2 = GPIO_ACCEL_INT2;
lsm303dlh_pdata_u8500.irq_m = GPIO_MAGNET_DRDY;
adp1653_pdata_u8500_uib.enable_gpio =
GPIO_CAMERA_FLASH_ENABLE;
}
ret = mop500_get_acc_id();
if (ret < 0)
printk(KERN_ERR " Failed to get Accelerometr chip ID\n");
else
lsm303dlh_pdata_u8500.chip_id = ret;
mop500_uib_i2c_add(2, mop500_i2c2_devices_u8500,
ARRAY_SIZE(mop500_i2c2_devices_u8500));
}
static int __init mop500_offchip_gpio_init(void)
{
if (machine_is_hrefv60() || machine_is_u8520() || machine_is_u9540())
ux500_offchip_gpio_init(&mop500_offchip_gpio_cfg);
return 0;
}
void __init mop500_stuib_init(void)
{
int ret;
if (machine_is_hrefv60() || machine_is_u8520() || machine_is_a9500()) {
tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO;
#ifdef CONFIG_U8500_FLASH
adp1653_pdata_u8500_uib.enable_gpio =
HREFV60_CAMERA_FLASH_ENABLE;
#endif
} else {
tsc_plat_device.cs_pin = GPIO_BU21013_CS;
#ifdef CONFIG_U8500_FLASH
adp1653_pdata_u8500_uib.enable_gpio =
GPIO_CAMERA_FLASH_ENABLE;
#endif
}
mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib,
ARRAY_SIZE(mop500_i2c0_devices_stuib));
mop500_uib_i2c_add(3, u8500_i2c3_devices_stuib,
ARRAY_SIZE(u8500_i2c3_devices_stuib));
if (machine_is_hrefv60() || machine_is_u8520() || machine_is_a9500()) {
lsm303dlh_pdata.irq_a1 = HREFV60_ACCEL_INT1_GPIO;
lsm303dlh_pdata.irq_a2 = HREFV60_ACCEL_INT2_GPIO;
lsm303dlh_pdata.irq_m = HREFV60_MAGNET_DRDY_GPIO;
} else if (machine_is_snowball()) {
lsm303dlh_pdata.irq_a1 = SNOWBALL_ACCEL_INT1_GPIO;
lsm303dlh_pdata.irq_a2 = SNOWBALL_ACCEL_INT2_GPIO;
lsm303dlh_pdata.irq_m = SNOWBALL_MAGNET_DRDY_GPIO;
} else {
lsm303dlh_pdata.irq_a1 = GPIO_ACCEL_INT1;
lsm303dlh_pdata.irq_a2 = GPIO_ACCEL_INT2;
lsm303dlh_pdata.irq_m = GPIO_MAGNET_DRDY;
}
ret = mop500_get_acc_id();
if (ret < 0)
printk(KERN_ERR " Failed to get Accelerometr chip ID\n");
else
lsm303dlh_pdata.chip_id = ret;
mop500_uib_i2c_add(2, mop500_i2c2_devices,
ARRAY_SIZE(mop500_i2c2_devices));
}
void __init mop500_pins_init(void)
{
nmk_config_pins(mop500_pins_common,
ARRAY_SIZE(mop500_pins_common));
ux500_pins_add(mop500_runtime_pins, ARRAY_SIZE(mop500_runtime_pins));
if (machine_is_hrefv60() || machine_is_u8520() || machine_is_u9540())
ux500_pins_add(mop500_runtime_pins_v60,
ARRAY_SIZE(mop500_runtime_pins_v60));
else if (machine_is_snowball())
ux500_pins_add(mop500_runtime_pins_snowball,
ARRAY_SIZE(mop500_runtime_pins_snowball));
else
ux500_pins_add(mop500_runtime_pins_pre_v60,
ARRAY_SIZE(mop500_runtime_pins_pre_v60));
if (machine_is_hrefv60() || machine_is_u8520() || machine_is_u9540())
nmk_config_pins(mop500_pins_hrefv60,
ARRAY_SIZE(mop500_pins_hrefv60));
else if (machine_is_snowball())
nmk_config_pins(snowball_pins,
ARRAY_SIZE(snowball_pins));
else
nmk_config_pins(mop500_pins_default,
ARRAY_SIZE(mop500_pins_default));
switch (pinsfor) {
case PINS_FOR_U9500:
nmk_config_pins(u9500_pins, ARRAY_SIZE(u9500_pins));
break;
case PINS_FOR_DEFAULT:
nmk_config_pins(u8500_pins, ARRAY_SIZE(u8500_pins));
default:
break;
}
suspend_set_pins_force_fn(mop500_pins_suspend_force,
mop500_pins_suspend_force_mux);
}
void __init mop500_pinmaps_init(void)
{
pinctrl_register_mappings(mop500_family_pinmap,
ARRAY_SIZE(mop500_family_pinmap));
pinctrl_register_mappings(mop500_pinmap,
ARRAY_SIZE(mop500_pinmap));
mop500_href_family_pinmaps_init();
if (machine_is_u8520())
pinctrl_register_mappings(ab8505_pinmap,
ARRAY_SIZE(ab8505_pinmap));
else
pinctrl_register_mappings(ab8500_pinmap,
ARRAY_SIZE(ab8500_pinmap));
}
void __init mop500_sdi_init(void)
{
/* v2 has a new version of this block that need to be forced */
u32 periphid = 0x10480180;
/* sdi2 on snowball is in ATL_B mode for FSMC (LAN) */
if (!machine_is_snowball())
db8500_add_sdi2(&mop500_sdi2_data, periphid);
/* On-board eMMC */
db8500_add_sdi4(&mop500_sdi4_data, periphid);
if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_snowball() || machine_is_u9540()) {
if (machine_is_hrefv60() || machine_is_u9540()) {
mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
sdi0_en = HREFV60_SDMMC_EN_GPIO;
sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
} else if (machine_is_u8520()) {
mop500_sdi0_data.gpio_cd = U8520_SDMMC_CD_GPIO;
sdi0_en = U8520_SDMMC_EN_GPIO;
sdi0_vsel = U8520_SDMMC_1V8_3V_GPIO;
} else if (machine_is_snowball()) {
mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
mop500_sdi0_data.cd_invert = true;
sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
}
sdi0_sdi1_configure();
}
/*
* On boards with the TC35892 GPIO expander, sdi0 and sdi1 will finally
* be added when the TC35892 initializes and calls
* mop500_sdi_tc35892_init() above.
*/
}
static int mmio_pin_cfg_init(struct mmio_platform_data *pdata)
{
int err;
struct mmio_board_data *extra = pdata->extra;
dev_dbg(pdata->dev , "Board %s() Enter\n", __func__);
extra->xshutdown_pins[PRIMARY_CAMERA].gpio = XSHUTDOWN_PRIMARY_SENSOR;
extra->xshutdown_pins[PRIMARY_CAMERA].active_high = 0;
extra->xshutdown_pins[PRIMARY_CAMERA].udelay = 500;
extra->xshutdown_pins[SECONDARY_CAMERA].active_high = 0;
extra->xshutdown_pins[SECONDARY_CAMERA].udelay = 500;
/* Update GPIO mappings according to board */
if (machine_is_hrefv60() || machine_is_u8520() || machine_is_u9540()) {
extra->xenon_charge = HREFV60_MMIO_XENON_CHARGE;
xshutdown_host[SECONDARY_CAMERA] = GPIO140_GPIO;
xshutdown_fw[SECONDARY_CAMERA] = GPIO140_IP_GPIO7;
xshutdown_disable[SECONDARY_CAMERA] =
GPIO140_GPIO | PIN_OUTPUT_LOW;
extra->xshutdown_pins[SECONDARY_CAMERA].gpio = 140;
} else {
extra->xenon_charge = GPIO_MMIO_XENON_CHARGE;
xshutdown_host[SECONDARY_CAMERA] = GPIO142_GPIO;
xshutdown_fw[SECONDARY_CAMERA] = GPIO142_IP_GPIO3;
xshutdown_disable[SECONDARY_CAMERA] =
GPIO142_GPIO | PIN_OUTPUT_LOW;
extra->xshutdown_pins[SECONDARY_CAMERA].gpio = 142;
}
/* Setup Xenon Charge */
err = gpio_request(extra->xenon_charge, "xenon charge");
if (err) {
dev_err(pdata->dev, "Error %d while requesting xenon charge\n",
err);
goto err_xenon_gpio_req;
}
err = gpio_direction_output(extra->xenon_charge, 0);
if (err) {
dev_err(pdata->dev, "Error %d while setting xenon charge in"
"output mode\n", err);
goto err_xenon_gpio_set_dir;
}
dev_dbg(pdata->dev , "Board %s() Exit\n", __func__);
return 0;
err_xenon_gpio_set_dir:
gpio_free(extra->xenon_charge);
err_xenon_gpio_req:
return err;
}
void mop500_regulator_init(void)
{
struct regulator_init_data *regulator;
/*
* Temporarily turn on Vaux2 on 8520 machine
*/
if (machine_is_u8520()) {
/* Vaux2 initialized to be on */
ab8500_modify_reg_init(AB8500_VAUX12REGU, 0x0f, 0x05);
/* Vaux2 always on */
regulator = &ab8500_ext_regulators[AB8500_LDO_AUX2];
regulator->constraints.always_on = 1;
}
/*
* Handle AB8500_EXT_SUPPLY2 on HREFP_V20_V50 boards (do it for
* all HREFP_V20 boards)
*/
if (cpu_is_u8500v20()) {
/* VextSupply2RequestCtrl = HP/OFF depending on VxRequest */
ab8500_modify_reg_init(AB8500_REGUREQUESTCTRL3, 0x01, 0x01);
/* VextSupply2SysClkReq1HPValid = SysClkReq1 controlled */
ab8500_modify_reg_init(AB8500_REGUSYSCLKREQ1HPVALID2,
0x20, 0x20);
/* VextSupply2 = force HP at initialization */
ab8500_modify_reg_init(AB8500_EXTSUPPLYREGU, 0x0c, 0x04);
/* enable VextSupply2 during platform active */
regulator = &ab8500_ext_regulators[AB8500_EXT_SUPPLY2];
regulator->constraints.always_on = 1;
/* disable VextSupply2 in suspend */
regulator = &ab8500_ext_regulators[AB8500_EXT_SUPPLY2];
regulator->constraints.state_mem.disabled = 1;
regulator->constraints.state_standby.disabled = 1;
/* enable VextSupply2 HW control (used in suspend) */
regulator->driver_data = (void *)&ab8500_ext_supply2;
}
}
/* Enable or disable micro sd card buffers on HREF */
static void control_level_shifter_for_microsd(int gpio_dir)
{
int gpio[2];
if (machine_is_u8540()) {
static struct regulator *regu_sdio;
if (gpio_dir) {
regu_sdio = regulator_get(&ux500_stm_device.dev,
"vmmc_io");
if (IS_ERR(regu_sdio)) {
regu_sdio = NULL;
STM_ERR("Failed to get regulator vmmc_io\n");
return;
}
regulator_disable(regu_sdio);
prcmu_set_sdmmc_psw(gpio_dir);
regulator_set_voltage(regu_sdio, 2750000, 3000000);
regulator_enable(regu_sdio);
usleep_range(3000, 4000);
} else if (regu_sdio) {
regulator_disable(regu_sdio);
regulator_put(regu_sdio);
regu_sdio = NULL;
}
return;
}
if (machine_is_hrefv60() || machine_is_u9540() || machine_is_a9500()) {
gpio[0] = HREFV60_SDMMC_EN_GPIO;
gpio[1] = HREFV60_SDMMC_1V8_3V_GPIO;
} else if (machine_is_u8520()) {
gpio[0] = U8520_SDMMC_EN_GPIO;
gpio[1] = U8520_SDMMC_1V8_3V_GPIO;
} else {
gpio[0] = MOP500_EGPIO(17);
gpio[1] = MOP500_EGPIO(18);
}
/* Select the default 2.9V and enable / disable level shifter */
gpio_direction_output(gpio[1], 0);
gpio_direction_output(gpio[0], gpio_dir);
}
/* Enable or disable micro sd card buffers on HREF */
static void control_level_shifter_for_microsd(int gpio_dir)
{
int gpio[2];
if (machine_is_hrefv60() || machine_is_u9540()) {
gpio[0] = HREFV60_SDMMC_EN_GPIO;
gpio[1] = HREFV60_SDMMC_1V8_3V_GPIO;
} else if (machine_is_u8520()) {
gpio[0] = U8520_SDMMC_EN_GPIO;
gpio[1] = U8520_SDMMC_1V8_3V_GPIO;
} else {
gpio[0] = MOP500_EGPIO(17);
gpio[1] = MOP500_EGPIO(18);
}
/* Select the default 2.9V and enable / disable level shifter */
gpio_direction_output(gpio[1], 0);
gpio_direction_output(gpio[0], gpio_dir);
}
static void mop500_pins_suspend_force(void)
{
if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_u9540())
sleep_pins_config_pm(mop500_pins_common_power_save_bank0_href60,
ARRAY_SIZE(mop500_pins_common_power_save_bank0_href60));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank0,
ARRAY_SIZE(mop500_pins_common_power_save_bank0));
sleep_pins_config_pm(mop500_pins_common_power_save_bank1,
ARRAY_SIZE(mop500_pins_common_power_save_bank1));
if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_u9540())
sleep_pins_config_pm(mop500_pins_common_power_save_bank2_href60,
ARRAY_SIZE(mop500_pins_common_power_save_bank2_href60));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank2,
ARRAY_SIZE(mop500_pins_common_power_save_bank2));
sleep_pins_config_pm(mop500_pins_common_power_save_bank3,
ARRAY_SIZE(mop500_pins_common_power_save_bank3));
if (pins_for_u9500() && uib_is_u8500uibr3())
sleep_pins_config_pm(mop500_pins_common_power_save_bank4_u9500_uibr3,
ARRAY_SIZE(mop500_pins_common_power_save_bank4_u9500_uibr3));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank4,
ARRAY_SIZE(mop500_pins_common_power_save_bank4));
if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_u9540())
sleep_pins_config_pm(mop500_pins_common_power_save_bank5_href60,
ARRAY_SIZE(mop500_pins_common_power_save_bank5_href60));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank5,
ARRAY_SIZE(mop500_pins_common_power_save_bank5));
if (pins_for_u9500())
sleep_pins_config_pm(mop500_pins_common_power_save_bank6_u9500,
ARRAY_SIZE(mop500_pins_common_power_save_bank6_u9500));
else if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_u9540())
sleep_pins_config_pm(mop500_pins_common_power_save_bank6_href60,
ARRAY_SIZE(mop500_pins_common_power_save_bank6_href60));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank6,
ARRAY_SIZE(mop500_pins_common_power_save_bank6));
if (pins_for_u9500())
sleep_pins_config_pm(mop500_pins_common_power_save_bank7_u9500,
ARRAY_SIZE(mop500_pins_common_power_save_bank7_u9500));
else if (machine_is_hrefv60() || machine_is_u8520() ||
machine_is_u9540())
sleep_pins_config_pm(mop500_pins_common_power_save_bank7_href60,
ARRAY_SIZE(mop500_pins_common_power_save_bank7_href60));
else
sleep_pins_config_pm(mop500_pins_common_power_save_bank7,
ARRAY_SIZE(mop500_pins_common_power_save_bank7));
sleep_pins_config_pm(mop500_pins_common_power_save_bank8,
ARRAY_SIZE(mop500_pins_common_power_save_bank8));
}
static int __init handle_display_devices(void)
{
bool video_mode = false;
struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data;
pr_debug("%s\n", __func__);
#ifdef CONFIG_FB_MCDE
(void)mcde_dss_register_notifier(&display_nb);
#endif
if (uib_is_u8500uibr3() && sony_port0.mode == MCDE_PORTMODE_VID)
video_mode = true;
/*
* display_initialized_during_boot will have the
* port_video_mode value + 1 if the display was initiated during boot,
* otherwise zero
*/
if (display_initialized_during_boot) {
/* restore video_mode value from boot */
u32 boot_video_mode = display_initialized_during_boot - 1;
/* if boot_video_mode not expected,
* clear already initiated flag */
if ((boot_video_mode == MCDE_PORTMODE_VID) != video_mode)
display_initialized_during_boot = 0;
}
/* Set powermode to STANDBY if startup graphics is executed */
if (display_initialized_during_boot) {
samsung_s6d16d0_display0.power_mode = MCDE_DISPLAY_PM_STANDBY;
sony_acx424akp_display0.power_mode = MCDE_DISPLAY_PM_STANDBY;
sharp_lq043t1_display0.power_mode = MCDE_DISPLAY_PM_STANDBY;
}
/* Display reset GPIO is different depending on reference boards */
if (machine_is_hrefv60() || machine_is_u8520()) {
samsung_s6d16d0_pdata0.reset_gpio = HREFV60_DISP1_RST_GPIO;
samsung_s6d16d0_pdata1.reset_gpio = HREFV60_DISP2_RST_GPIO;
} else {
samsung_s6d16d0_pdata0.reset_gpio = MOP500_DISP1_RST_GPIO;
samsung_s6d16d0_pdata1.reset_gpio = MOP500_DISP2_RST_GPIO;
}
/* Initialize all needed clocks*/
if (!display_initialized_during_boot) {
struct clk *clk_dsi_pll;
struct clk *clk_hdmi;
struct clk *clk_tv;
u32 freq;
/*
* The TV CLK is used as parent for the
* DSI LP clock.
*/
clk_tv = clk_get(&ux500_mcde_device.dev, "tv");
if (TV_FREQ_HZ != clk_round_rate(clk_tv, TV_FREQ_HZ))
pr_warning("%s: TV_CLK freq differs %ld\n", __func__,
clk_round_rate(clk_tv, TV_FREQ_HZ));
clk_set_rate(clk_tv, TV_FREQ_HZ);
clk_put(clk_tv);
/*
* The HDMI CLK is used as parent for the
* DSI HS clock.
*/
clk_hdmi = clk_get(&ux500_mcde_device.dev, "hdmi");
if (HDMI_FREQ_HZ != clk_round_rate(clk_hdmi, HDMI_FREQ_HZ))
pr_warning("%s: HDMI freq differs %ld\n", __func__,
clk_round_rate(clk_hdmi, HDMI_FREQ_HZ));
clk_set_rate(clk_hdmi, HDMI_FREQ_HZ);
clk_put(clk_hdmi);
/*
* The DSI PLL CLK is used as DSI PLL for direct freq for
* link 2. Link 0/1 is then divided with 1/2/4 from this freq.
*/
freq = video_mode ? DSI_PLL_FREQ_HZ_VID : DSI_PLL_FREQ_HZ_CMD;
clk_dsi_pll = clk_get(&ux500_mcde_device.dev, "dsipll");
if (freq != clk_round_rate(clk_dsi_pll, freq))
pr_warning("%s: DSI_PLL freq differs %ld\n", __func__,
clk_round_rate(clk_dsi_pll, freq));
clk_set_rate(clk_dsi_pll, freq);
clk_put(clk_dsi_pll);
}
/* MCDE pixelfetchwtrmrk levels per overlay */
pdata->pixelfetchwtrmrk[0] = video_mode ? 128 : 48; /* LCD 32bpp */
pdata->pixelfetchwtrmrk[1] = video_mode ? 128 : 64; /* LCD 16bpp */
pdata->pixelfetchwtrmrk[2] = 128; /* HDMI 32bpp */
pdata->pixelfetchwtrmrk[3] = 192; /* HDMI 16bpp */
/* Not all STUIBs supports VSYNC, disable vsync for STUIB */
if (uib_is_stuib()) {
/* Samsung display on STUIB */
samsung_s6d16d0_display0.port->sync_src = MCDE_SYNCSRC_OFF;
samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CCW;
(void)mcde_display_device_register(&samsung_s6d16d0_display0);
} else if (uib_is_u8500uib()) {
/* Samsung display on U8500UIB */
samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CW;
(void)mcde_display_device_register(&samsung_s6d16d0_display0);
} else if (uib_is_u8500uibr3()) {
/* Sony display on U8500UIBV3 */
sony_acx424akp_display0_pdata.reset_gpio = HREFV60_DISP1_RST_GPIO;
(void)mcde_display_device_register(&sony_acx424akp_display0);
} else {
sharp_lq043t1_display0_pdata.reset_gpio = HREFV60_DISP1_RST_GPIO;
(void)mcde_display_device_register(&sharp_lq043t1_display0);
}
/* Display reset GPIO is different depending on reference boards */
if (uib_is_stuib())
(void)mcde_display_device_register(&samsung_s6d16d0_display1);
#if defined(CONFIG_U8500_TV_OUTPUT_AV8100)
INIT_DELAYED_WORK_DEFERRABLE(&work_dispreg_hdmi,
delayed_work_dispreg_hdmi);
schedule_delayed_work(&work_dispreg_hdmi,
msecs_to_jiffies(DISPREG_HDMI_DELAY));
#endif
return 0;
}
static int __init handle_display_devices_in_u8500(void)
{
struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data;
pr_debug("%s\n", __func__);
#ifdef CONFIG_FB_MCDE
(void)mcde_dss_register_notifier(&display_nb);
#endif
/* Set powermode to STANDBY if startup graphics is executed */
if (display_initialized_during_boot) {
samsung_s6d16d0_display0.power_mode = MCDE_DISPLAY_PM_STANDBY;
sony_acx424akp_display0.power_mode = MCDE_DISPLAY_PM_STANDBY;
}
/* Display reset GPIO is different depending on reference boards */
if (machine_is_hrefv60() || machine_is_u8520() || machine_is_u9540()) {
samsung_s6d16d0_pdata0.reset_gpio = HREFV60_DISP1_RST_GPIO;
samsung_s6d16d0_pdata1.reset_gpio = HREFV60_DISP2_RST_GPIO;
} else {
samsung_s6d16d0_pdata0.reset_gpio = MOP500_DISP1_RST_GPIO;
samsung_s6d16d0_pdata1.reset_gpio = MOP500_DISP2_RST_GPIO;
}
/* Initialize all needed clocks*/
if (!display_initialized_during_boot) {
struct clk *clk_dsi_pll;
struct clk *clk_hdmi;
struct clk *clk_tv;
/*
* The TV CLK is used as parent for the
* DSI LP clock.
*/
clk_tv = clk_get(&ux500_mcde_device.dev, "tv");
if (TV_FREQ_HZ != clk_round_rate(clk_tv, TV_FREQ_HZ))
pr_warning("%s: TV_CLK freq differs %ld\n", __func__,
clk_round_rate(clk_tv, TV_FREQ_HZ));
clk_set_rate(clk_tv, TV_FREQ_HZ);
clk_put(clk_tv);
/*
* The HDMI CLK is used as parent for the
* DSI HS clock.
*/
clk_hdmi = clk_get(&ux500_mcde_device.dev, "hdmi");
if (HDMI_FREQ_HZ != clk_round_rate(clk_hdmi, HDMI_FREQ_HZ))
pr_warning("%s: HDMI freq differs %ld\n", __func__,
clk_round_rate(clk_hdmi, HDMI_FREQ_HZ));
clk_set_rate(clk_hdmi, HDMI_FREQ_HZ);
clk_put(clk_hdmi);
/*
* The DSI PLL CLK is used as DSI PLL for direct freq for
* link 2. Link 0/1 is then divided with 1/2/4 from this freq.
*/
clk_dsi_pll = clk_get(&ux500_mcde_device.dev, "dsihs2");
if (DSI_PLL_FREQ_HZ != clk_round_rate(clk_dsi_pll,
DSI_PLL_FREQ_HZ))
pr_warning("%s: DSI_PLL freq differs %ld\n", __func__,
clk_round_rate(clk_dsi_pll, DSI_PLL_FREQ_HZ));
clk_set_rate(clk_dsi_pll, DSI_PLL_FREQ_HZ);
clk_put(clk_dsi_pll);
}
/* MCDE pixelfetchwtrmrk levels per overlay */
pdata->pixelfetchwtrmrk[0] = 48; /* LCD 32 bpp */
pdata->pixelfetchwtrmrk[1] = 64; /* LCD 16 bpp */
pdata->pixelfetchwtrmrk[2] = 128; /* HDMI 32 bpp */
pdata->pixelfetchwtrmrk[3] = 192; /* HDMI 16 bpp */
/* Not all STUIBs supports VSYNC, disable vsync for STUIB */
if (uib_is_stuib()) {
/* Samsung display on STUIB */
samsung_s6d16d0_display0.port->sync_src = MCDE_SYNCSRC_OFF;
samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CCW;
(void)mcde_display_device_register(&samsung_s6d16d0_display0);
} else if (uib_is_u8500uib()) {
/* Samsung display on U8500UIB */
samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CW;
(void)mcde_display_device_register(&samsung_s6d16d0_display0);
} else if (uib_is_u8500uibr3()) {
/* Sony display on U8500UIBV3 */
(void)mcde_display_device_register(&sony_acx424akp_display0);
} else {
WARN_ON("Unknown UI board");
}
/* Display reset GPIO is different depending on reference boards */
if (uib_is_stuib())
(void)mcde_display_device_register(&samsung_s6d16d0_display1);
#if defined(CONFIG_U8500_TV_OUTPUT_AV8100)
INIT_DELAYED_WORK_DEFERRABLE(&work_dispreg_hdmi,
delayed_work_dispreg_hdmi);
schedule_delayed_work(&work_dispreg_hdmi,
msecs_to_jiffies(DISPREG_HDMI_DELAY));
#endif
return 0;
}
