static void
squidboy(Apic* apic)
{
// iprint("Hello Squidboy\n");
machinit();
fpsavealloc();
mmuinit();
cpuidentify();
cpuidprint();
checkmtrr();
apic->online = 1;
coherence();
lapicinit(apic);
lapiconline();
syncclock();
timersinit();
fpoff();
lock(&active);
active.machs |= 1<<m->machno;
unlock(&active);
while(!active.thunderbirdsarego)
microdelay(100);
schedinit();
}
void
main(void)
{
memset(edata, 0, (ulong)end-(ulong)edata);
conf.nmach = 1;
machinit();
confinit();
xinit();
trapinit();
mmuinit();
plan9iniinit();
hwintrinit();
clockinit();
timerinit();
console();
quotefmtinstall();
printinit();
cpuidprint();
print("\nPlan 9 from Bell Labs\n");
procinit0();
initseg();
timersinit();
links();
chandevreset();
pageinit();
swapinit();
sharedseginit();
fpsave(&initfp);
initfp.fpscr = 0;
userinit();
schedinit();
}
static void
squidboy(Apic* apic)
{
// iprint("Hello Squidboy\n");
machinit();
mmuinit();
cpuidentify();
cpuidprint();
checkmtrr();
lock(&mprdthilock);
mprdthi |= (1<<apic->apicno)<<24;
unlock(&mprdthilock);
lapicinit(apic);
lapiconline();
syncclock();
timersinit();
fpoff();
lock(&active);
active.machs |= 1<<m->machno;
unlock(&active);
while(!active.thunderbirdsarego)
microdelay(100);
schedinit();
}
void
mach0init(void)
{
conf.nmach = 1;
MACHP(0) = (Mach*)CPU0MACH;
m->pdb = (ulong*)CPU0PDB;
m->gdt = (Segdesc*)CPU0GDT;
machinit();
active.machs = 1;
active.exiting = 0;
}
void
mach0init(void)
{
conf.nmach = 1;
MACHP(0) = mach0m;
m->machno = 0;
m->pdb = mach0pdb;
m->gdt = mach0gdt;
machinit();
active.machs = 1;
active.exiting = 0;
}
void
main(void)
{
extern char edata[], end[];
uint rev;
okay(1);
m = (Mach*)MACHADDR;
memset(edata, 0, end - edata); /* clear bss */
machinit();
mmuinit1();
optionsinit("/boot/boot boot");
quotefmtinstall();
ataginit((Atag*)BOOTARGS);
confinit(); /* figures out amount of memory */
xinit();
uartconsinit();
screeninit();
print("\nPlan 9 from Bell Labs\n");
rev = getfirmware();
print("firmware: rev %d\n", rev);
if(rev < Minfirmrev){
print("Sorry, firmware (start.elf) must be at least rev %d (%s)\n",
Minfirmrev, Minfirmdate);
for(;;)
;
}
trapinit();
clockinit();
printinit();
timersinit();
cpuidprint();
archreset();
procinit0();
initseg();
links();
chandevreset(); /* most devices are discovered here */
pageinit();
swapinit();
userinit();
gpiomeminit();
schedinit();
assert(0); /* shouldn't have returned */
}
void
main(void)
{
hwrpb = (Hwrpb*)0x10000000;
hwrpb = (Hwrpb*)(KZERO|hwrpb->phys);
arginit();
machinit();
options();
ioinit();
clockinit();
confinit();
archinit();
xinit();
memholes();
if(i8237alloc != nil)
i8237alloc();
mmuinit();
if(arch->coreinit)
arch->coreinit();
trapinit();
screeninit();
printinit();
/* it's now safe to print */
/* dumpopts(); /* DEBUG */
i8250console();
quotefmtinstall();
print("\nPlan 9\n");
cpuidprint();
if(arch->corehello)
arch->corehello();
procinit0();
initseg();
timersinit();
links();
chandevreset();
pageinit();
swapinit();
savefpregs(&initfp);
initfp.fpstatus = 0x68028000;
userinit();
schedinit();
}
void
main(void)
{
machinit();
trapinit();
quotefmtinstall();
confinit();
xinit();
mmuinit();
intrinit();
clockinit();
printinit();
screeninit();
ioinit();
doc("ioinit...");
ns16552install();
poolsizeinit();
doc("ns16552install...");
kbdinit();
doc("kbdinit...");
cacheinit();
doc("cacheinit...");
procinit();
doc("procinit...");
putphys(MID, 0x1F<<16); /* enable arbitration */
links();
doc("links");
chandevreset();
doc("chandevreset...");
print("\nInferno Operating System\n");
print("%s-%s \n\n",VERSION, conffile);
print("JIT Compilation Mode = %d\n",cflag);
userinit();
doc("userinit...");
/* clear pending processor interrupts */
putphys(PROCINTCLR, (~0<<17)|(1<<15));
print("berore schedinit\n");
schedinit();
}
/* l.s has already zeroed Mach, which now contains our stack. */
void
mach0init(void)
{
if (m == 0) {
serialputc('?');
serialputc('m');
}
conf.nmach = 0;
m->machno = 0;
machaddr[0] = m;
lock(&testlock); /* hold this forever */
machinit();
active.exiting = 0;
l1cache->wbse(&active, sizeof active);
up = nil;
}
void
main(void)
{
machinit();
options();
archinit();
quotefmtinstall();
confinit();
cpminit();
xinit();
poolsizeinit();
trapinit();
mmuinit();
printinit();
uartinstall();
serialconsole();
doc("screeninit");
screeninit();
doc("kbdinit");
kbdinit();
doc("clockinit");
clockinit();
doc("procinit");
procinit();
cpuidprint();
doc("links");
links();
doc("chandevreset");
chandevreset();
eve = strdup("inferno");
print("\nInferno %s\n", VERSION);
print("Vita Nuova\n");
print("conf %s (%lud) jit %d\n\n",conffile, kerndate, cflag);
doc("userinit");
userinit();
doc("schedinit");
schedinit();
}
void
main(void)
{
mmuinvalidate();
/* zero out bss */
memset(edata, 0, end-edata);
/* point to Mach structure */
m = (Mach*)MACHADDR;
memset(m, 0, sizeof(Mach));
m->ticks = 1;
active.machs = 1;
rs232power(1);
quotefmtinstall();
iprint("\nPlan 9 bitsy kernel\n");
confinit();
xinit();
mmuinit();
machinit();
trapinit();
sa1110_uartsetup(1);
dmainit();
screeninit();
printinit(); /* from here on, print works, before this we need iprint */
clockinit();
procinit0();
initseg();
links();
chandevreset();
pageinit();
swapinit();
userinit();
powerinit();
schedinit();
}
void
main(int argc, char **argv)
{
int i, nets = 0;
char *ann;
rfork(RFNOTEG);
formatinit();
machinit();
conf.confdev = "n"; /* Devnone */
ARGBEGIN{
case 'a': /* announce on this net */
ann = EARGF(usage());
if (nets >= Maxnets) {
fprint(2, "%s: too many networks to announce: %s\n",
argv0, ann);
exits("too many nets");
}
annstrs[nets++] = ann;
break;
case 'c': /* use new, faster cache layout */
oldcachefmt = 0;
break;
case 'f': /* enter configuration mode first */
conf.configfirst++;
break;
case 'm': /* name device-map file */
conf.devmap = EARGF(usage());
break;
default:
usage();
break;
}ARGEND
if (argc != 1)
usage();
conf.confdev = argv[0]; /* config string for dev holding full config */
Binit(&bin, 0, OREAD);
confinit();
print("\nPlan 9 %d-bit cached-worm file server with %d-deep indir blks\n",
sizeof(Off)*8 - 1, NIBLOCK);
printsizes();
qlock(&reflock);
qunlock(&reflock);
serveq = newqueue(1000, "9P service"); /* tunable */
raheadq = newqueue(1000, "readahead"); /* tunable */
mbinit();
netinit();
scsiinit();
files = malloc(conf.nfile * sizeof *files);
for(i=0; i < conf.nfile; i++) {
qlock(&files[i]);
qunlock(&files[i]);
}
wpaths = malloc(conf.nwpath * sizeof(*wpaths));
uid = malloc(conf.nuid * sizeof(*uid));
gidspace = malloc(conf.gidspace * sizeof(*gidspace));
authinit();
print("iobufinit\n");
iobufinit();
arginit();
boottime = time(nil);
print("sysinit\n");
sysinit();
/*
* Ethernet i/o processes
*/
netstart();
/*
* read ahead processes
*/
newproc(rahead, 0, "rah");
/*
* server processes
*/
for(i=0; i < conf.nserve; i++)
newproc(serve, 0, "srv");
/*
* worm "dump" copy process
*/
newproc(wormcopy, 0, "wcp");
/*
* processes to read the console
*/
consserve();
/*
* "sync" copy process
* this doesn't return.
*/
procsetname("scp");
synccopy();
}
/*
* called on a cpu other than 0 from cpureset in l.s,
* from _vrst in lexception.s.
* mmu and l1 (and system-wide l2) caches and coherency (smpon) are on,
* but interrupts are disabled.
* our mmu is using an exact copy of cpu0's l1 page table
* as it was after userinit ran.
*/
void
cpustart(void)
{
int ms;
ulong *evp;
Power *pwr;
up = nil;
if (active.machs & (1<<m->machno)) {
serialputc('?');
serialputc('r');
panic("cpu%d: resetting after start", m->machno);
}
assert(m->machno != 0);
errata();
cortexa9cachecfg();
memdiag(&testmem);
machinit(); /* bumps nmach, adds bit to machs */
machoff(m->machno); /* not ready to go yet */
/* clock signals and scu are system-wide and already on */
clockshutdown(); /* kill any watch-dog timer */
trapinit();
clockinit(); /* sets loop delay */
timersinit();
cpuidprint();
/*
* notify cpu0 that we're up so it can proceed to l1diag.
*/
evp = (ulong *)soc.exceptvec; /* magic */
*evp = m->machno;
coherence();
l1diag(); /* contend with other cpus to verify sanity */
/*
* pwr->noiopwr == 0
* pwr->detect == 0x1ff (default, all disabled)
*/
pwr = (Power *)soc.power;
assert(pwr->gatests == MASK(7)); /* everything has power */
/*
* 8169 has to initialise before we get past this, thus cpu0
* has to schedule processes first.
*/
if (Debug)
iprint("cpu%d: waiting for 8169\n", m->machno);
for (ms = 0; !l1ptstable.word && ms < 5000; ms += 10) {
delay(10);
cachedinvse(&l1ptstable.word, sizeof l1ptstable.word);
}
if (!l1ptstable.word)
iprint("cpu%d: 8169 unreasonably slow; proceeding\n", m->machno);
/* now safe to copy cpu0's l1 pt in mmuinit */
mmuinit(); /* update our l1 pt from cpu0's */
fpon();
machon(m->machno); /* now ready to go and be scheduled */
if (Debug)
iprint("cpu%d: scheding\n", m->machno);
schedinit();
panic("cpu%d: schedinit returned", m->machno);
}
/*
* entered from l.s with mmu enabled.
*
* we may have to realign the data segment; apparently 5l -H0 -R4096
* does not pad the text segment. on the other hand, we may have been
* loaded by another kernel.
*
* be careful not to touch the data segment until we know it's aligned.
*/
void
main(Mach* mach)
{
extern char bdata[], edata[], end[], etext[];
static ulong vfy = 0xcafebabe;
m = mach;
if (vfy != 0xcafebabe)
memmove(bdata, etext, edata - bdata);
if (vfy != 0xcafebabe) {
wave('?');
panic("misaligned data segment");
}
memset(edata, 0, end - edata); /* zero bss */
vfy = 0;
wave('9');
machinit();
archreset();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
archconsole();
wave(' ');
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
/* set memsize before xinit */
confinit();
/* xinit would print if it could */
xinit();
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockintr) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
trapinit();
clockinit();
printinit();
uartkirkwoodconsole();
/* only now can we print */
print("from Bell Labs\n\n");
#ifdef CRYPTOSANDBOX
print("sandbox: 64K at physical %#lux, mapped to 0xf10b0000\n",
PADDR((uintptr)sandbox & ~(BY2PG-1)));
#endif
archconfinit();
cpuidprint();
timersinit();
procinit0();
initseg();
links();
chandevreset(); /* most devices are discovered here */
spiprobe();
pageinit();
swapinit();
userinit();
schedinit();
panic("schedinit returned");
}
int
main(int argc, char *argv[])
{
char root[NAMEMAX * 5];
int r, fd;
if (rootfs() < 0) {
return ERR;
}
fd = open("/dev", O_RDONLY|O_CREATE,
ATTR_wr|ATTR_rd|ATTR_dir);
if (fd < 0) {
return ERR;
}
close(fd);
fd = open("/mnt", O_RDONLY|O_CREATE,
ATTR_rd|ATTR_dir);
if (fd < 0) {
return ERR;
}
close(fd);
fd = open("/bin", O_RDONLY|O_CREATE,
ATTR_rd|ATTR_dir);
if (fd < 0) {
return ERR;
}
close(fd);
r = machinit();
if (r != OK) {
return ERR;
}
/*
matrix(1000, 1, 1000);
*/
while (true) {
printf("root: ");
r = readline(root, sizeof(root));
if (r < 0) {
printf("error reading!\n");
return ERR;
}
printf("mountfat %s /mnt\n", root);
r = mountfat(root, "/mnt");
if (r == OK) {
break;
} else {
printf("error mounting root!\n");
}
}
printf("bind /mnt/bin /bin\n");
bind("/mnt/bin", "/bin");
printf("exec /bin/init\n");
r = exec("/bin/init", argc, argv);
printf("error exec /bin/init: %i\n", r);
return r;
}
void
main(void)
{
// int i;
extern char bdata[], edata[], end[], etext[];
static ulong vfy = 0xcafebabe;
/* l.s has already printed "Plan 9 from Be" */
// m = mach; /* now done in l.s */
/* realign data seg; apparently -H0 -R4096 does not pad the text seg */
if (vfy != 0xcafebabe) {
// wave('<'); wave('-');
memmove(bdata, etext, edata - bdata);
}
/*
* once data segment is in place, always zero bss since we may
* have been loaded by another Plan 9 kernel.
*/
memset(edata, 0, end - edata); /* zero BSS */
cacheuwbinv();
l2cacheuwbinv();
if (vfy != 0xcafebabe)
panic("data segment misaligned");
vfy = 0;
wave('l');
machinit();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
trapinit(); /* so confinit can probe memory to size it */
confinit(); /* figures out amount of memory */
/* xinit prints (if it can), so finish up the banner here. */
delay(500);
iprint("l Labs\n\n");
delay(500);
xinit();
mainmem->flags |= POOL_ANTAGONISM /* | POOL_PARANOIA */ ;
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockinit) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
archreset(); /* configure clock signals */
clockinit(); /* start clocks */
timersinit();
watchdoginit();
delay(250); /* let uart catch up */
printinit();
// kbdenable();
cpuidprint();
// chkmissing();
procinit0();
initseg();
dmainit();
links();
conf.monitor = 1;
screeninit();
chandevreset(); /* most devices are discovered here */
// i8250console(); /* too early; see init0 */
pageinit();
swapinit();
userinit();
schedinit();
}
