예제 #1
0
void mainboard_romstage_entry(struct romstage_params *params)
{
	post_code(0x31);
	/* Fill out PEI DATA */
	mainboard_fill_pei_data(params->pei_data);
	romstage_common(params);
}
예제 #2
0
파일: raminit_mrc.c 프로젝트: af00/coreboot
void perform_raminit(int s3resume)
{
	int cbmem_was_initted;
	struct pei_data pei_data;

	/* Prepare USB controller early in S3 resume */
	if (!mainboard_should_reset_usb(s3resume))
		enable_usb_bar();

	mainboard_fill_pei_data(&pei_data);

	post_code(0x3a);
	pei_data.boot_mode = s3resume ? 2 : 0;
	timestamp_add_now(TS_BEFORE_INITRAM);
	sdram_initialize(&pei_data);
	cbmem_was_initted = !cbmem_recovery(s3resume);
	if (!s3resume)
		save_mrc_data(&pei_data);

	if (s3resume && !cbmem_was_initted) {
		/* Failed S3 resume, reset to come up cleanly */
		outb(0x6, 0xcf9);
		halt();
	}
}
예제 #3
0
void mainboard_romstage_entry(struct romstage_params *rp)
{
	struct pei_data pei_data;

	post_code(0x31);

	if (rp->power_state->prev_sleep_state != SLEEP_STATE_S3)
		google_chromeec_kbbacklight(100);

	printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());

	/* Ensure the EC and PD are in the right mode for recovery */
	google_chromeec_early_init();

	/* Initialize GPIOs */
	init_gpios(mainboard_gpio_config);

	/* Fill out PEI DATA */
	memset(&pei_data, 0, sizeof(pei_data));
	mainboard_fill_pei_data(&pei_data);
	mainboard_fill_spd_data(&pei_data);
	rp->pei_data = &pei_data;

	/* Initalize memory */
	romstage_common(rp);

	/* Bring SSD out of reset */
	set_gpio(SAMUS_GPIO_SSD_RESET_L, GPIO_OUT_HIGH);

	/*
	 * Enable PP3300_AUTOBAHN_EN after initial GPIO setup
	 * to prevent possible brownout.
	 */
	set_gpio(SAMUS_GPIO_PP3300_AUTOBAHN_EN, GPIO_OUT_HIGH);
}
예제 #4
0
void broadwell_run_reference_code(void)
{
	int ret, dummy;
	struct pei_data pei_data;
	pei_wrapper_entry_t entry;

	memset(&pei_data, 0, sizeof(pei_data));
	mainboard_fill_pei_data(&pei_data);
	broadwell_fill_pei_data(&pei_data);

	pei_data.boot_mode = acpi_is_wakeup_s3() ? SLEEP_STATE_S3 : 0;
	pei_data.saved_data = (void *) &dummy;

	entry = load_reference_code();
	if (entry == NULL) {
		printk(BIOS_ERR, "Reference code not found\n");
		return;
	}

	/* Call into reference code. */
	ret = entry(&pei_data);
	if (ret != 0) {
		printk(BIOS_ERR, "Reference code returned %d\n", ret);
		return;
	}
}
예제 #5
0
파일: romstage.c 프로젝트: bitpick/coreboot
void mainboard_romstage_entry(struct romstage_params *params)
{
    /* Fill out PEI DATA */
    mainboard_fill_pei_data(params->pei_data);
    mainboard_fill_spd_data(params->pei_data);
    /* Initliaze memory */
    romstage_common(params);
}
예제 #6
0
void mainboard_romstage_entry(struct romstage_params *params)
{
	/* Ensure the EC and PD are in the right mode for recovery */
	google_chromeec_early_init();

	early_config_gpio();

	/* Fill out PEI DATA */
	mainboard_fill_pei_data(params->pei_data);
	mainboard_fill_spd_data(params->pei_data);
	/* Initliaze memory */
	romstage_common(params);
}
예제 #7
0
파일: refcode.c 프로젝트: tidatida/coreboot
static pei_wrapper_entry_t load_reference_code(void)
{
	struct prog prog = {
		.name = CONFIG_CBFS_PREFIX "/refcode",
	};
	struct rmod_stage_load refcode = {
		.cbmem_id = CBMEM_ID_REFCODE,
		.prog = &prog,
	};

	if (acpi_is_wakeup_s3()) {
		return load_refcode_from_cache();
	}

	if (load_refcode_from_vboot(&refcode) ||
		load_refcode_from_cbfs(&refcode))
			return NULL;

	/* Cache loaded reference code. */
	cache_refcode(&refcode);

	return prog_entry(&prog);
}

void broadwell_run_reference_code(void)
{
	int ret, dummy;
	struct pei_data pei_data;
	pei_wrapper_entry_t entry;

	memset(&pei_data, 0, sizeof(pei_data));
	mainboard_fill_pei_data(&pei_data);
	broadwell_fill_pei_data(&pei_data);

	pei_data.boot_mode = acpi_slp_type;
	pei_data.saved_data = (void *) &dummy;

	entry = load_reference_code();
	if (entry == NULL) {
		printk(BIOS_ERR, "Reference code not found\n");
		return;
	}

	/* Call into reference code. */
	ret = entry(&pei_data);
	if (ret != 0) {
		printk(BIOS_ERR, "Reference code returned %d\n", ret);
		return;
	}
}
예제 #8
0
파일: romstage.c 프로젝트: AdriDlu/coreboot
void mainboard_romstage_entry(struct romstage_params *rp)
{
	struct pei_data pei_data;

	/* Initialize GPIOs */
	init_gpios(mainboard_gpio_config);

	/* Fill out PEI DATA */
	memset(&pei_data, 0, sizeof(pei_data));
	mainboard_fill_pei_data(&pei_data);
	rp->pei_data = &pei_data;

	/* Initialize memory */
	romstage_common(rp);
}
예제 #9
0
void mainboard_romstage_entry(struct romstage_params *params)
{
	/* Ensure the EC and PD are in the right mode for recovery */
	google_chromeec_early_init();

	/* Turn on keyboard backlight to indicate we are booting */
	if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
		google_chromeec_kbbacklight(100);

	early_config_gpio();

	/* Fill out PEI DATA */
	mainboard_fill_pei_data(params->pei_data);
	mainboard_fill_spd_data(params->pei_data);
	/* Initliaze memory */
	romstage_common(params);
}
예제 #10
0
void mainboard_romstage_entry(struct romstage_params *rp)
{
	struct pei_data pei_data;

	post_code(0x32);

	/* Initialize GPIOs */
	init_gpios(mainboard_gpio_config);

	/* Fill out PEI DATA */
	memset(&pei_data, 0, sizeof(pei_data));
	mainboard_fill_pei_data(&pei_data);
	mainboard_fill_spd_data(&pei_data);
	rp->pei_data = &pei_data;

	/* Call into the real romstage main with this board's attributes. */
	romstage_common(rp);

	if (IS_ENABLED(CONFIG_CHROMEOS))
		save_chromeos_gpios();
}
예제 #11
0
void mainboard_romstage_entry(struct romstage_params *params)
{
#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT
	/* Turn on keyboard backlight to indicate we are booting */
	if (params->power_state->prev_sleep_state != ACPI_S3)
		google_chromeec_kbbacklight(25);
#endif
	/* Get SPD index */
	gpio_t spd_gpios[] = {
		GPIO_MEM_CONFIG_0,
		GPIO_MEM_CONFIG_1,
		GPIO_MEM_CONFIG_2,
		GPIO_MEM_CONFIG_3,
	};
	params->pei_data->mem_cfg_id =
			gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
	/* Fill out PEI DATA */
	mainboard_fill_pei_data(params->pei_data);
	mainboard_fill_spd_data(params->pei_data);
	/* Initialize memory */
	romstage_common(params);
}
예제 #12
0
void mainboard_romstage_entry(struct romstage_params *params)
{
	/* PCH_MEM_CFG[3:0] */
	gpio_t spd_gpios[] = {
		GPIO_MEM_CONFIG_0,
		GPIO_MEM_CONFIG_1,
		GPIO_MEM_CONFIG_2,
		GPIO_MEM_CONFIG_3,
	};

	/* Ensure the EC and PD are in the right mode for recovery */
	google_chromeec_early_init();

	early_config_gpio();

	params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios,
							ARRAY_SIZE(spd_gpios));
	/* Fill out PEI DATA */
	mainboard_fill_pei_data(params->pei_data);
	mainboard_fill_spd_data(params->pei_data);
	/* Initliaze memory */
	romstage_common(params);
}
예제 #13
0
void mainboard_romstage_entry(struct romstage_params *rp)
{
	struct pei_data pei_data;

	post_code(0x32);

	/* Ensure the EC is in the right mode for recovery */
	google_chromeec_early_init();

	/* Initialize GPIOs */
	init_gpios(mainboard_gpio_config);

	/* Fill out PEI DATA */
	memset(&pei_data, 0, sizeof(pei_data));
	mainboard_fill_pei_data(&pei_data);
	mainboard_fill_spd_data(&pei_data);
	rp->pei_data = &pei_data;

	/* Call into the real romstage main with this board's attributes. */
	romstage_common(rp);

	/* Do variant-specific (read: Samus) init */
	variant_romstage_entry(rp);
}
예제 #14
0
파일: sdram.c 프로젝트: 01hyang/u-boot
int dram_init(void)
{
	struct pei_data _pei_data __aligned(8);
	struct pei_data *pei_data = &_pei_data;
	struct udevice *dev, *me_dev, *pch_dev;
	struct chipset_power_state ps;
	const void *spd_data;
	int ret, size;

	memset(pei_data, '\0', sizeof(struct pei_data));

	/* Print ME state before MRC */
	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
	if (ret)
		return ret;
	intel_me_status(me_dev);

	/* Save ME HSIO version */
	ret = uclass_first_device(UCLASS_PCH, &pch_dev);
	if (ret)
		return ret;
	if (!pch_dev)
		return -ENODEV;
	power_state_get(pch_dev, &ps);

	intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);

	broadwell_fill_pei_data(pei_data);
	mainboard_fill_pei_data(pei_data);

	ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
	if (ret)
		return ret;
	if (!dev)
		return -ENODEV;
	size = 256;
	ret = mrc_locate_spd(dev, size, &spd_data);
	if (ret)
		return ret;
	memcpy(pei_data->spd_data[0][0], spd_data, size);
	memcpy(pei_data->spd_data[1][0], spd_data, size);

	ret = prepare_mrc_cache(pei_data);
	if (ret)
		debug("prepare_mrc_cache failed: %d\n", ret);

	debug("PEI version %#x\n", pei_data->pei_version);
	ret = mrc_common_init(dev, pei_data, true);
	if (ret)
		return ret;
	debug("Memory init done\n");

	ret = sdram_find(dev);
	if (ret)
		return ret;
	gd->ram_size = gd->arch.meminfo.total_32bit_memory;
	debug("RAM size %llx\n", (unsigned long long)gd->ram_size);

	debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,
	      pei_data->data_to_save);
	/* S3 resume: don't save scrambler seed or MRC data */
	if (pei_data->boot_mode != SLEEP_STATE_S3) {
		/*
		 * This will be copied to SDRAM in reserve_arch(), then written
		 * to SPI flash in mrccache_save()
		 */
		gd->arch.mrc_output = (char *)pei_data->data_to_save;
		gd->arch.mrc_output_len = pei_data->data_to_save_size;
	}
	gd->arch.pei_meminfo = pei_data->meminfo;

	return 0;
}