void namco_54xx_write(UINT8 data) { int cpunum = mame_find_cpu_index(Machine, CPUTAG_54XX); if (cpunum == -1) return; timer_call_after_resynch(NULL, data, namco_54xx_latch_callback); cpunum_set_input_line(Machine, cpunum, 0, ASSERT_LINE); // The execution time of one instruction is ~4us, so we must make sure to // give the cpu time to poll the /IRQ input before we clear it. // The input clock to the 06XX interface chip is 64H, that is // 18432000/6/64 = 48kHz, so it makes sense for the irq line to be // asserted for one clock cycle ~= 21us. timer_set(ATTOTIME_IN_USEC(21), NULL, cpunum, namco_54xx_irq_clear); }
static TIMER_CALLBACK( setirq_callback ) { int cpunum; switch(param) { case YM2151_ASSERT: irqstate |= 1|4; break; case YM2151_CLEAR: irqstate &= ~1; break; case YM2151_ACK: irqstate &= ~4; break; case CPU_ASSERT: irqstate |= 2; // also used by t5182_sharedram_semaphore_main_r break; case CPU_CLEAR: irqstate &= ~2; break; } cpunum = mame_find_cpu_index(machine, CPUTAG_T5182); if (cpunum == -1) return; if (irqstate == 0) /* no IRQs pending */ cpunum_set_input_line(machine, cpunum,0,CLEAR_LINE); else /* IRQ pending */ cpunum_set_input_line(machine, cpunum,0,ASSERT_LINE); }
static void c128_set_m8502_read_handler(UINT16 start, UINT16 end, read8_handler rh) { int cpunum; cpunum = mame_find_cpu_index("m8502"); memory_install_read8_handler(cpunum, ADDRESS_SPACE_PROGRAM, start, end, 0, 0, rh); }