예제 #1
0
void
hfcd_l1cmd(struct IsdnCardState *cs, int msg, void *arg)
{
	char tmp[32];
	switch(msg) {
		case PH_RESET_REQ:
			cs->writeisac(cs, HFCD_STATES, HFCD_LOAD_STATE | 3); /* HFC ST 3 */
			udelay(6);
			cs->writeisac(cs, HFCD_STATES, 3); /* HFC ST 2 */
			cs->hw.hfcD.mst_m |= HFCD_MASTER;
			cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
			cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION);
			manl1_msg(cs, PH_POWERUP_CNF, NULL);
			break;
		case PH_ENABLE_REQ:
			cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION);
			break;
		case PH_DEACT_ACK:
			cs->hw.hfcD.mst_m &= ~HFCD_MASTER;
			cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
			break;
		case PH_INFO3_REQ:
			cs->hw.hfcD.mst_m |= HFCD_MASTER;
			cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m);
			break;
#if 0
		case PH_TESTLOOP_REQ:
			u_char val = 0;
			if (1 & (int) arg)
				val |= 0x0c;
			if (2 & (int) arg)
				val |= 0x3;
			if (test_bit(HW_IOM1, &cs->HW_Flags)) {
				/* IOM 1 Mode */
				if (!val) {
					cs->writeisac(cs, ISAC_SPCR, 0xa);
					cs->writeisac(cs, ISAC_ADF1, 0x2);
				} else {
					cs->writeisac(cs, ISAC_SPCR, val);
					cs->writeisac(cs, ISAC_ADF1, 0xa);
				}
			} else {
				/* IOM 2 Mode */
				cs->writeisac(cs, ISAC_SPCR, val);
				if (val)
					cs->writeisac(cs, ISAC_ADF1, 0x8);
				else
					cs->writeisac(cs, ISAC_ADF1, 0x0);
			}
			break;
#endif
		default:
			if (cs->debug & L1_DEB_WARN) {
				sprintf(tmp, "hfcd_l1cmd unknown %4x", msg);
				debugl1(cs, tmp);
			}
			break;
	}
}
예제 #2
0
static void
amd7930_new_ph(struct IsdnCardState *cs)
{
	switch (amd7930_get_liu_state(0)) {
	        case 3:
			manl1_msg(cs, PH_POWERUP_CNF, NULL);
                        break;

	        case 7:
			manl1_msg(cs, PH_I4_P8_IND, NULL);
			break;

	        case 8:
			manl1_msg(cs, PH_RSYNC_IND, NULL);
			break;
	}
}
예제 #3
0
static void
hfcd_bh(struct IsdnCardState *cs)
{
/*	struct PStack *stptr;
*/
	if (!cs)
		return;
#if 0	
	if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) {
		if (cs->debug)
			debugl1(cs, "D-Channel Busy cleared");
		stptr = cs->stlist;
		while (stptr != NULL) {
			stptr->l1.l1l2(stptr, PH_PAUSE_CNF, NULL);
			stptr = stptr->next;
		}
	}
#endif
	if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
		switch (cs->ph_state) {
			case (0):
				manl1_msg(cs, PH_RESET_IND, NULL);
				break;
			case (3):
				manl1_msg(cs, PH_DEACT_IND, NULL);
				break;
			case (8):
				manl1_msg(cs, PH_RSYNC_IND, NULL);
				break;
			case (6):
				manl1_msg(cs, PH_INFO2_IND, NULL);
				break;
			case (7):
				manl1_msg(cs, PH_I4_P8_IND, NULL);
				break;
			default:
				break;
		}
	}
	if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
		DChannel_proc_rcv(cs);
	if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
		DChannel_proc_xmt(cs);
}