int write_si_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
struct si_controller* si = (struct si_controller*)opaque;
uint32_t reg = si_reg(address);
switch (reg)
{
case SI_DRAM_ADDR_REG:
masked_write(&si->regs[SI_DRAM_ADDR_REG], value, mask);
break;
case SI_PIF_ADDR_RD64B_REG:
masked_write(&si->regs[SI_PIF_ADDR_RD64B_REG], value, mask);
dma_si_read(si);
break;
case SI_PIF_ADDR_WR64B_REG:
masked_write(&si->regs[SI_PIF_ADDR_WR64B_REG], value, mask);
dma_si_write(si);
break;
case SI_STATUS_REG:
si->regs[SI_STATUS_REG] &= ~0x1000;
clear_rcp_interrupt(si->r4300, MI_INTR_SI);
break;
}
return 0;
}
void write_ai_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
struct ai_controller* ai = (struct ai_controller*)opaque;
uint32_t reg = ai_reg(address);
switch (reg)
{
case AI_LEN_REG:
masked_write(&ai->regs[AI_LEN_REG], value, mask);
if (ai->regs[AI_LEN_REG] != 0) {
fifo_push(ai);
}
else {
/* stop sound */
}
return;
case AI_STATUS_REG:
clear_rcp_interrupt(ai->mi, MI_INTR_AI);
return;
case AI_BITRATE_REG:
case AI_DACRATE_REG:
/* lazy audio format setting */
if ((ai->regs[reg]) != (value & mask))
ai->samples_format_changed = 1;
masked_write(&ai->regs[reg], value, mask);
return;
}
masked_write(&ai->regs[reg], value, mask);
}
int write_ai_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
struct ai_controller* ai = (struct ai_controller*)opaque;
uint32_t reg = ai_reg(address);
unsigned int freq,delay=0;
switch (reg)
{
case AI_LEN_REG:
masked_write(&ai->regs[AI_LEN_REG], value, mask);
audio.aiLenChanged();
freq = ROM_PARAMS.aidacrate / (ai->regs[AI_DACRATE_REG]+1);
if (freq)
delay = (unsigned int) (((unsigned long long)ai->regs[AI_LEN_REG]*ai->vi->delay*ROM_PARAMS.vilimit)/(freq*4));
if (ai->regs[AI_STATUS_REG] & 0x40000000) // busy
{
ai->fifo[1].delay = delay;
ai->fifo[1].length = ai->regs[AI_LEN_REG];
ai->regs[AI_STATUS_REG] |= 0x80000000;
}
else
{
ai->fifo[0].delay = delay;
ai->fifo[0].length = ai->regs[AI_LEN_REG];
update_count();
add_interupt_event(AI_INT, delay);
ai->regs[AI_STATUS_REG] |= 0x40000000;
}
return 0;
case AI_STATUS_REG:
clear_rcp_interrupt(ai->r4300, MI_INTR_AI);
return 0;
case AI_DACRATE_REG:
if ((ai->regs[AI_DACRATE_REG] & mask) != (value & mask))
{
masked_write(&ai->regs[AI_DACRATE_REG], value, mask);
audio.aiDacrateChanged(ROM_PARAMS.systemtype);
}
return 0;
}
masked_write(&ai->regs[reg], value, mask);
return 0;
}
int write_rsp_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
struct rsp_core* sp = (struct rsp_core*)opaque;
uint32_t reg = rsp_reg(address);
switch(reg)
{
case SP_STATUS_REG:
update_sp_status(sp, value & mask);
case SP_DMA_FULL_REG:
case SP_DMA_BUSY_REG:
return 0;
}
masked_write(&sp->regs[reg], value, mask);
switch(reg)
{
case SP_RD_LEN_REG:
dma_sp_write(sp);
break;
case SP_WR_LEN_REG:
dma_sp_read(sp);
break;
case SP_SEMAPHORE_REG:
sp->regs[SP_SEMAPHORE_REG] = 0;
break;
}
return 0;
}
int write_dpc_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
struct rdp_core* dp = (struct rdp_core*)opaque;
uint32_t reg = dpc_reg(address);
switch(reg)
{
case DPC_STATUS_REG:
if (update_dpc_status(dp, value & mask) != 0)
do_SP_Task(dp->sp);
case DPC_CURRENT_REG:
case DPC_CLOCK_REG:
case DPC_BUFBUSY_REG:
case DPC_PIPEBUSY_REG:
case DPC_TMEM_REG:
return 0;
}
masked_write(&dp->dpc_regs[reg], value, mask);
switch(reg)
{
case DPC_START_REG:
dp->dpc_regs[DPC_CURRENT_REG] = dp->dpc_regs[DPC_START_REG];
break;
case DPC_END_REG:
gfx.processRDPList();
signal_rcp_interrupt(dp->r4300, MI_INTR_DP);
break;
}
return 0;
}
int write_rsp_regs2(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
struct rsp_core* sp = (struct rsp_core*)opaque;
uint32_t reg = rsp_reg2(address);
masked_write(&sp->regs2[reg], value, mask);
return 0;
}
int write_rsp_mem(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
struct rsp_core* sp = (struct rsp_core*)opaque;
uint32_t addr = rsp_mem_address(address);
masked_write(&sp->mem[addr], value, mask);
return 0;
}
int write_dps_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
struct rdp_core* dp = (struct rdp_core*)opaque;
uint32_t reg = dps_reg(address);
masked_write(&dp->dps_regs[reg], value, mask);
return 0;
}
int write_ri_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
struct ri_controller* ri = (struct ri_controller*)opaque;
uint32_t reg = ri_reg(address);
masked_write(&ri->regs[reg], value, mask);
return 0;
}
void write_sram(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
struct sram* sram = (struct sram*)opaque;
uint8_t* mem = sram->istorage->data(sram->storage);
address &= SRAM_ADDR_MASK;
masked_write((uint32_t*)(mem + address), value, mask);
sram->istorage->save(sram->storage);
}
void write_ri_regs(struct ri_controller* ri, uint32_t address, uint32_t value, uint32_t mask)
{
const uint32_t reg = ri_reg(address);
masked_write(&ri->regs[reg], value, mask);
}