int __init init_display_devices(void) { int ret; ret = fb_register_client(&framebuffer_nb); if (ret) pr_warning("Failed to register framebuffer notifier\n"); ret = mcde_dss_register_notifier(&display_nb); if (ret) pr_warning("Failed to register dss notifier\n"); #ifdef CONFIG_DISPLAY_GENERIC_PRIMARY if (display_initialized_during_boot) generic_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; ret = mcde_display_device_register(&generic_display0); if (ret) pr_warning("Failed to register generic display device 0\n"); #endif #ifdef CONFIG_DISPLAY_AV8100_TERTIARY INIT_DELAYED_WORK_DEFERRABLE(&work_dispreg_hdmi, delayed_work_dispreg_hdmi); schedule_delayed_work(&work_dispreg_hdmi, msecs_to_jiffies(DISPREG_HDMI_DELAY)); #endif return ret; }
static int __init handle_display_devices_in_u9540(void) { struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data; pr_debug("%s\n", __func__); #ifdef CONFIG_FB_MCDE (void)mcde_dss_register_notifier(&display_nb); #endif /* Set powermode to STANDBY if startup graphics is executed */ if (display_initialized_during_boot) sony_acx424akp_display0.power_mode = MCDE_DISPLAY_PM_ON; /* MCDE pixelfetchwtrmrk levels per overlay */ pdata->pixelfetchwtrmrk[0] = 64; /* LCD 32 bpp */ pdata->pixelfetchwtrmrk[1] = 96; /* LCD 16 bpp */ pdata->pixelfetchwtrmrk[2] = 192; /* HDMI 32 bpp */ pdata->pixelfetchwtrmrk[3] = 256; /* HDMI 16 bpp */ sony_acx424akp_display0_pdata.reset_gpio = UIB_9540_DISP1_RST_GPIO; (void)mcde_display_device_register(&sony_acx424akp_display0); return 0; }
int __init init_janice_display_devices(void) { struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data; int ret; ret = mcde_dss_register_notifier(&display_nb); if (ret) pr_warning("Failed to register dss notifier\n"); if (display_initialized_during_boot) { generic_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; janice_dpi_pri_display_info.platform_enabled = 1; } /* * The pixclock setting is not used within MCDE. The clock is * setup elsewhere. But the pixclock value is visible in user * space. */ janice_dpi_pri_display_info.video_mode.pixclock /= port0.phy.dpi.clock_div; /* MCDE pixelfetchwtrmrk levels per overlay */ { #if 1 /* 16 bit overlay */ #define BITS_PER_WORD (4 * 64) u32 fifo = (1024*8 - 8 * BITS_PER_WORD) / 3; fifo &= ~(BITS_PER_WORD - 1); pdata->pixelfetchwtrmrk[0] = fifo * 2 / 32; /* LCD 32bpp */ pdata->pixelfetchwtrmrk[1] = fifo * 1 / 16; /* LCD 16bpp */ #else /* 24 bit overlay */ u32 fifo = (1024*8 - 8 * BITS_PER_WORD) / 7; fifo &= ~(BITS_PER_WORD - 1); pdata->pixelfetchwtrmrk[0] = fifo * 4 / 32; /* LCD 32bpp */ pdata->pixelfetchwtrmrk[1] = fifo * 3 / 24; /* LCD 24bpp */ #endif } pdata->update_opp = update_mcde_opp; ret = mcde_display_device_register(&generic_display0); if (ret) pr_warning("Failed to register generic display device 0\n"); #ifndef CONFIG_HAS_EARLYSUSPEND dpi_pins = ux500_pins_get("mcde-dpi"); if (!dpi_pins) return -EINVAL; #endif return ret; }
int __init init_gavini_display_devices(void) { int ret; ret = fb_register_client(&framebuffer_nb); if (ret) pr_warning("Failed to register framebuffer notifier\n"); ret = mcde_dss_register_notifier(&display_nb); if (ret) pr_warning("Failed to register dss notifier\n"); if (display_initialized_during_boot) { generic_display0.power_mode = MCDE_DISPLAY_PM_ON; gavini_dpi_pri_display_info.platform_enabled = 1; } /* * The pixclock setting is not used within MCDE. The clock is * setup elsewhere. But the pixclock value is visible in user * space. */ gavini_dpi_pri_display_info.video_mode.pixclock /= port0.phy.dpi.clock_div; ret = mcde_display_device_register(&generic_display0); if (ret) pr_warning("Failed to register generic display device 0\n"); #ifndef CONFIG_HAS_EARLYSUSPEND dpi_pins = ux500_pins_get("mcde-dpi"); if (!dpi_pins) return -EINVAL; #endif return ret; }
int __init init_display_devices(void) { int ret; #ifdef CONFIG_DISPLAY_GENERIC_DSI_PRIMARY_VSYNC struct i2c_adapter *i2c0; #endif ret = fb_register_client(&framebuffer_nb); if (ret) pr_warning("Failed to register framebuffer notifier\n"); ret = mcde_dss_register_notifier(&display_nb); if (ret) pr_warning("Failed to register dss notifier\n"); #ifdef CONFIG_DISPLAY_GENERIC_PRIMARY if (machine_is_hrefv60()) generic_display0_pdata.reset_gpio = HREFV60_DISP1_RST_GPIO; else generic_display0_pdata.reset_gpio = EGPIO_PIN_15; #ifdef CONFIG_DISPLAY_GENERIC_DSI_PRIMARY_VSYNC i2c0 = i2c_get_adapter(0); if (i2c0) { /* * U8500-UIB has the TC35893 at 0x44 on I2C0, the * ST-UIB has not. */ ret = i2c_smbus_xfer(i2c0, 0x44, 0, I2C_SMBUS_WRITE, 0, I2C_SMBUS_QUICK, NULL); i2c_put_adapter(i2c0); /* ret == 0 => U8500 UIB connected */ generic_display0.synchronized_update = (ret == 0); } #endif if (display_initialized_during_boot) generic_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; ret = mcde_display_device_register(&generic_display0); if (ret) pr_warning("Failed to register generic display device 0\n"); #endif #ifdef CONFIG_DISPLAY_GENERIC_DSI_SECONDARY if (machine_is_hrefv60()) generic_subdisplay_pdata.reset_gpio = HREFV60_DISP2_RST_GPIO; else generic_subdisplay_pdata.reset_gpio = EGPIO_PIN_14; ret = mcde_display_device_register(&generic_subdisplay); if (ret) pr_warning("Failed to register generic sub display device\n"); #endif #ifdef CONFIG_DISPLAY_AV8100_TERTIARY INIT_DELAYED_WORK_DEFERRABLE(&work_dispreg_hdmi, delayed_work_dispreg_hdmi); schedule_delayed_work(&work_dispreg_hdmi, msecs_to_jiffies(DISPREG_HDMI_DELAY)); #endif #ifdef CONFIG_DISPLAY_AB8500_TERTIARY ret = mcde_display_device_register(&tvout_ab8500_display); if (ret) pr_warning("Failed to register ab8500 tvout device\n"); #endif return ret; }
static int __init handle_display_devices(void) { bool video_mode = false; struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data; pr_debug("%s\n", __func__); #ifdef CONFIG_FB_MCDE (void)mcde_dss_register_notifier(&display_nb); #endif if (uib_is_u8500uibr3() && sony_port0.mode == MCDE_PORTMODE_VID) video_mode = true; /* * display_initialized_during_boot will have the * port_video_mode value + 1 if the display was initiated during boot, * otherwise zero */ if (display_initialized_during_boot) { /* restore video_mode value from boot */ u32 boot_video_mode = display_initialized_during_boot - 1; /* if boot_video_mode not expected, * clear already initiated flag */ if ((boot_video_mode == MCDE_PORTMODE_VID) != video_mode) display_initialized_during_boot = 0; } /* Set powermode to STANDBY if startup graphics is executed */ if (display_initialized_during_boot) { samsung_s6d16d0_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; sony_acx424akp_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; sharp_lq043t1_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; } /* Display reset GPIO is different depending on reference boards */ if (machine_is_hrefv60() || machine_is_u8520()) { samsung_s6d16d0_pdata0.reset_gpio = HREFV60_DISP1_RST_GPIO; samsung_s6d16d0_pdata1.reset_gpio = HREFV60_DISP2_RST_GPIO; } else { samsung_s6d16d0_pdata0.reset_gpio = MOP500_DISP1_RST_GPIO; samsung_s6d16d0_pdata1.reset_gpio = MOP500_DISP2_RST_GPIO; } /* Initialize all needed clocks*/ if (!display_initialized_during_boot) { struct clk *clk_dsi_pll; struct clk *clk_hdmi; struct clk *clk_tv; u32 freq; /* * The TV CLK is used as parent for the * DSI LP clock. */ clk_tv = clk_get(&ux500_mcde_device.dev, "tv"); if (TV_FREQ_HZ != clk_round_rate(clk_tv, TV_FREQ_HZ)) pr_warning("%s: TV_CLK freq differs %ld\n", __func__, clk_round_rate(clk_tv, TV_FREQ_HZ)); clk_set_rate(clk_tv, TV_FREQ_HZ); clk_put(clk_tv); /* * The HDMI CLK is used as parent for the * DSI HS clock. */ clk_hdmi = clk_get(&ux500_mcde_device.dev, "hdmi"); if (HDMI_FREQ_HZ != clk_round_rate(clk_hdmi, HDMI_FREQ_HZ)) pr_warning("%s: HDMI freq differs %ld\n", __func__, clk_round_rate(clk_hdmi, HDMI_FREQ_HZ)); clk_set_rate(clk_hdmi, HDMI_FREQ_HZ); clk_put(clk_hdmi); /* * The DSI PLL CLK is used as DSI PLL for direct freq for * link 2. Link 0/1 is then divided with 1/2/4 from this freq. */ freq = video_mode ? DSI_PLL_FREQ_HZ_VID : DSI_PLL_FREQ_HZ_CMD; clk_dsi_pll = clk_get(&ux500_mcde_device.dev, "dsipll"); if (freq != clk_round_rate(clk_dsi_pll, freq)) pr_warning("%s: DSI_PLL freq differs %ld\n", __func__, clk_round_rate(clk_dsi_pll, freq)); clk_set_rate(clk_dsi_pll, freq); clk_put(clk_dsi_pll); } /* MCDE pixelfetchwtrmrk levels per overlay */ pdata->pixelfetchwtrmrk[0] = video_mode ? 128 : 48; /* LCD 32bpp */ pdata->pixelfetchwtrmrk[1] = video_mode ? 128 : 64; /* LCD 16bpp */ pdata->pixelfetchwtrmrk[2] = 128; /* HDMI 32bpp */ pdata->pixelfetchwtrmrk[3] = 192; /* HDMI 16bpp */ /* Not all STUIBs supports VSYNC, disable vsync for STUIB */ if (uib_is_stuib()) { /* Samsung display on STUIB */ samsung_s6d16d0_display0.port->sync_src = MCDE_SYNCSRC_OFF; samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CCW; (void)mcde_display_device_register(&samsung_s6d16d0_display0); } else if (uib_is_u8500uib()) { /* Samsung display on U8500UIB */ samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CW; (void)mcde_display_device_register(&samsung_s6d16d0_display0); } else if (uib_is_u8500uibr3()) { /* Sony display on U8500UIBV3 */ sony_acx424akp_display0_pdata.reset_gpio = HREFV60_DISP1_RST_GPIO; (void)mcde_display_device_register(&sony_acx424akp_display0); } else { sharp_lq043t1_display0_pdata.reset_gpio = HREFV60_DISP1_RST_GPIO; (void)mcde_display_device_register(&sharp_lq043t1_display0); } /* Display reset GPIO is different depending on reference boards */ if (uib_is_stuib()) (void)mcde_display_device_register(&samsung_s6d16d0_display1); #if defined(CONFIG_U8500_TV_OUTPUT_AV8100) INIT_DELAYED_WORK_DEFERRABLE(&work_dispreg_hdmi, delayed_work_dispreg_hdmi); schedule_delayed_work(&work_dispreg_hdmi, msecs_to_jiffies(DISPREG_HDMI_DELAY)); #endif return 0; }
int __init init_codina_display_devices(void) { int ret; struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data; ret = mcde_dss_register_notifier(&display_nb); if (ret) pr_warning("Failed to register dss notifier\n"); if (display_initialized_during_boot) { generic_display0.power_mode = MCDE_DISPLAY_PM_ON; codina_dpi_pri_display_info.platform_enabled = 1; } /* * The pixclock setting is not used within MCDE. The clock is * setup elsewhere. But the pixclock value is visible in user * space. */ if (lcd_type == LCD_PANEL_TYPE_SMD) { port0.phy.dpi.clock_div = 2; port0.phy.dpi.lcd_freq = PRCMU_DPI_CLK_SMD_FREQ; codina_dpi_pri_display_info.video_mode.pixclock = (int)(1e+12 * (1.0 / PRCMU_DPI_CLK_SMD_FREQ)); } else { port0.phy.dpi.clock_div = 1; port0.phy.dpi.lcd_freq = PRCMU_DPI_CLK_SHARP_FREQ; codina_dpi_pri_display_info.video_mode.pixclock = (int)(1e+12 * (1.0 / PRCMU_DPI_CLK_SHARP_FREQ)); } codina_dpi_pri_display_info.video_mode.pixclock /= port0.phy.dpi.clock_div; /* MCDE pixelfetchwtrmrk levels per overlay */ { #if 1 /* * The pixel fetcher FIFO is 128*64bit = 8192bits = 1024bytes. * Overlay 0 is assumed 32bpp and overlay 1 is assumed 16bpp */ pdata->pixelfetchwtrmrk[0] = 160; /* 160 -> 160px*32bpp/8=640bytes */ pdata->pixelfetchwtrmrk[1] = 192; /* 192 -> 192px*16bpp/8=384bytes */ #else /* 24 bit overlay */ u32 fifo = (1024*8 - 8 * BITS_PER_WORD) / 7; fifo &= ~(BITS_PER_WORD - 1); pdata->pixelfetchwtrmrk[0] = fifo * 4 / 32; /* LCD 32bpp */ pdata->pixelfetchwtrmrk[1] = fifo * 3 / 24; /* LCD 24bpp */ #endif } pdata->update_opp = update_mcde_opp; if (lcd_type == LCD_PANEL_TYPE_SMD){ generic_display0.name = LCD_DRIVER_NAME_WS2401; codina_dpi_pri_display_info.video_mode.hsw = 10; codina_dpi_pri_display_info.video_mode.hbp = 8; codina_dpi_pri_display_info.video_mode.hfp = 8; codina_dpi_pri_display_info.video_mode.vsw = 2; codina_dpi_pri_display_info.video_mode.vbp = 8; codina_dpi_pri_display_info.video_mode.vfp = 18; } else { generic_display0.name = LCD_DRIVER_NAME_S6D27A1; codina_dpi_pri_display_info.video_mode.hsw = 2; codina_dpi_pri_display_info.video_mode.hbp = 63; codina_dpi_pri_display_info.video_mode.hfp = 63; codina_dpi_pri_display_info.video_mode.vsw = 2; codina_dpi_pri_display_info.video_mode.vbp = 11; codina_dpi_pri_display_info.video_mode.vfp = 10; } ret = mcde_display_device_register(&generic_display0); if (ret) pr_warning("Failed to register generic display device 0\n"); dpi_pins = ux500_pins_get("mcde-dpi"); if (!dpi_pins) return -EINVAL; error: return ret; }
static int __init handle_display_devices_in_u8500(void) { struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data; pr_debug("%s\n", __func__); #ifdef CONFIG_FB_MCDE (void)mcde_dss_register_notifier(&display_nb); #endif /* Set powermode to STANDBY if startup graphics is executed */ if (display_initialized_during_boot) { samsung_s6d16d0_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; sony_acx424akp_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; } /* Display reset GPIO is different depending on reference boards */ if (machine_is_hrefv60() || machine_is_u8520() || machine_is_u9540()) { samsung_s6d16d0_pdata0.reset_gpio = HREFV60_DISP1_RST_GPIO; samsung_s6d16d0_pdata1.reset_gpio = HREFV60_DISP2_RST_GPIO; } else { samsung_s6d16d0_pdata0.reset_gpio = MOP500_DISP1_RST_GPIO; samsung_s6d16d0_pdata1.reset_gpio = MOP500_DISP2_RST_GPIO; } /* Initialize all needed clocks*/ if (!display_initialized_during_boot) { struct clk *clk_dsi_pll; struct clk *clk_hdmi; struct clk *clk_tv; /* * The TV CLK is used as parent for the * DSI LP clock. */ clk_tv = clk_get(&ux500_mcde_device.dev, "tv"); if (TV_FREQ_HZ != clk_round_rate(clk_tv, TV_FREQ_HZ)) pr_warning("%s: TV_CLK freq differs %ld\n", __func__, clk_round_rate(clk_tv, TV_FREQ_HZ)); clk_set_rate(clk_tv, TV_FREQ_HZ); clk_put(clk_tv); /* * The HDMI CLK is used as parent for the * DSI HS clock. */ clk_hdmi = clk_get(&ux500_mcde_device.dev, "hdmi"); if (HDMI_FREQ_HZ != clk_round_rate(clk_hdmi, HDMI_FREQ_HZ)) pr_warning("%s: HDMI freq differs %ld\n", __func__, clk_round_rate(clk_hdmi, HDMI_FREQ_HZ)); clk_set_rate(clk_hdmi, HDMI_FREQ_HZ); clk_put(clk_hdmi); /* * The DSI PLL CLK is used as DSI PLL for direct freq for * link 2. Link 0/1 is then divided with 1/2/4 from this freq. */ clk_dsi_pll = clk_get(&ux500_mcde_device.dev, "dsihs2"); if (DSI_PLL_FREQ_HZ != clk_round_rate(clk_dsi_pll, DSI_PLL_FREQ_HZ)) pr_warning("%s: DSI_PLL freq differs %ld\n", __func__, clk_round_rate(clk_dsi_pll, DSI_PLL_FREQ_HZ)); clk_set_rate(clk_dsi_pll, DSI_PLL_FREQ_HZ); clk_put(clk_dsi_pll); } /* MCDE pixelfetchwtrmrk levels per overlay */ pdata->pixelfetchwtrmrk[0] = 48; /* LCD 32 bpp */ pdata->pixelfetchwtrmrk[1] = 64; /* LCD 16 bpp */ pdata->pixelfetchwtrmrk[2] = 128; /* HDMI 32 bpp */ pdata->pixelfetchwtrmrk[3] = 192; /* HDMI 16 bpp */ /* Not all STUIBs supports VSYNC, disable vsync for STUIB */ if (uib_is_stuib()) { /* Samsung display on STUIB */ samsung_s6d16d0_display0.port->sync_src = MCDE_SYNCSRC_OFF; samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CCW; (void)mcde_display_device_register(&samsung_s6d16d0_display0); } else if (uib_is_u8500uib()) { /* Samsung display on U8500UIB */ samsung_s6d16d0_display0.orientation = MCDE_DISPLAY_ROT_90_CW; (void)mcde_display_device_register(&samsung_s6d16d0_display0); } else if (uib_is_u8500uibr3()) { /* Sony display on U8500UIBV3 */ (void)mcde_display_device_register(&sony_acx424akp_display0); } else { WARN_ON("Unknown UI board"); } /* Display reset GPIO is different depending on reference boards */ if (uib_is_stuib()) (void)mcde_display_device_register(&samsung_s6d16d0_display1); #if defined(CONFIG_U8500_TV_OUTPUT_AV8100) INIT_DELAYED_WORK_DEFERRABLE(&work_dispreg_hdmi, delayed_work_dispreg_hdmi); schedule_delayed_work(&work_dispreg_hdmi, msecs_to_jiffies(DISPREG_HDMI_DELAY)); #endif return 0; }
int __init init_kyle_display_devices(void) { int ret; struct clk *clk_dsi_pll; struct clk *clk_hdmi; struct clk *clk_tv; struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data; unsigned long dsi_pll_freq; ret = mcde_dss_register_notifier(&display_nb); if (ret) ; if (display_initialized_during_boot) { hva40wv1_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; nt35512_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; } else { hva40wv1_display0.power_mode = MCDE_DISPLAY_PM_OFF; nt35512_display0.power_mode = MCDE_DISPLAY_PM_OFF; } /* we need to initialize all the clocks used */ /* * The TV CLK is used as parent for the * DSI LP clock. */ clk_tv = clk_get(&ux500_mcde_device.dev, "tv"); if (TV_FREQ_HZ != clk_round_rate(clk_tv, TV_FREQ_HZ)) // printk(KERN_ERR "%s: TV_CLK freq differs %ld\n", __func__, ; clk_set_rate(clk_tv, TV_FREQ_HZ); clk_put(clk_tv); /* * The HDMI CLK is used as parent for the * DSI HS clock. */ clk_hdmi = clk_get(&ux500_mcde_device.dev, "hdmi"); if (HDMI_FREQ_HZ != clk_round_rate(clk_hdmi, HDMI_FREQ_HZ)) // printk(KERN_ERR "%s: HDMI freq differs %ld\n", __func__, ; clk_set_rate(clk_hdmi, HDMI_FREQ_HZ); clk_put(clk_hdmi); /* * The DSI PLL CLK is used as DSI PLL for direct freq for * link 2. Link 0/1 is then divided with 1/2/4 from this freq. */ if (lcd_type == LCD_PANEL_TYPE_HVA40WV1) dsi_pll_freq = DSI_PLL_FREQ_HZ_HVA40WV1; else if (lcd_type == LCD_PANEL_TYPE_NT35512) dsi_pll_freq = DSI_PLL_FREQ_HZ_NT35512; else { ; ret = -ENODEV; goto error; } clk_dsi_pll = clk_get(&ux500_mcde_device.dev, "dsipll"); if (dsi_pll_freq != clk_round_rate(clk_dsi_pll, dsi_pll_freq)) // printk(KERN_ERR "%s: DSI_PLL freq differs %ld\n", __func__, ; clk_set_rate(clk_dsi_pll, dsi_pll_freq); clk_put(clk_dsi_pll); /* MCDE pixelfetchwtrmrk levels per overlay */ { #define BITS_PER_WORD (4 * 64) #if 1 /* 16 bit overlay */ u32 fifo = (1024*8 - 8 * BITS_PER_WORD) / 3; fifo &= ~(BITS_PER_WORD - 1); pdata->pixelfetchwtrmrk[0] = fifo * 2 / 32; /* LCD 32bpp */ pdata->pixelfetchwtrmrk[1] = fifo * 1 / 16; /* LCD 16bpp */ #else /* 24 bit overlay */ u32 fifo = (1024*8 - 8 * BITS_PER_WORD) / 7; fifo &= ~(BITS_PER_WORD - 1); pdata->pixelfetchwtrmrk[0] = fifo * 4 / 32; /* LCD 32bpp */ pdata->pixelfetchwtrmrk[1] = fifo * 3 / 24; /* LCD 24bpp */ #endif } if (lcd_type == LCD_PANEL_TYPE_HVA40WV1) ret = mcde_display_device_register(&hva40wv1_display0); else ret = mcde_display_device_register(&nt35512_display0); /* increased OPP required for DSI Mode panel */ pdata->update_opp = update_mcde_opp; if (ret) ; error: return ret; }
int __init init_golden_display_devices(void) { struct mcde_platform_data *pdata = ux500_mcde_device.dev.platform_data; int ret; struct clk *clk_dsi_pll; struct clk *clk_hdmi; struct clk *clk_tv; ret = mcde_dss_register_notifier(&display_nb); if (ret) printk(KERN_ERR "Failed to register dss notifier\n"); if (display_initialized_during_boot) generic_display0.power_mode = MCDE_DISPLAY_PM_STANDBY; else generic_display0.power_mode = MCDE_DISPLAY_PM_OFF; /* we need to initialize all the clocks used */ /* * The TV CLK is used as parent for the * DSI LP clock. */ clk_tv = clk_get(&ux500_mcde_device.dev, "tv"); if (TV_FREQ_HZ != clk_round_rate(clk_tv, TV_FREQ_HZ)) printk(KERN_ERR "%s: TV_CLK freq differs %ld\n", __func__, clk_round_rate(clk_tv, TV_FREQ_HZ)); clk_set_rate(clk_tv, TV_FREQ_HZ); clk_put(clk_tv); /* * The HDMI CLK is used as parent for the * DSI HS clock. */ clk_hdmi = clk_get(&ux500_mcde_device.dev, "hdmi"); if (HDMI_FREQ_HZ != clk_round_rate(clk_hdmi, HDMI_FREQ_HZ)) printk(KERN_ERR "%s: HDMI freq differs %ld\n", __func__, clk_round_rate(clk_hdmi, HDMI_FREQ_HZ)); clk_set_rate(clk_hdmi, HDMI_FREQ_HZ); clk_put(clk_hdmi); /* * The DSI PLL CLK is used as DSI PLL for direct freq for * link 2. Link 0/1 is then divided with 1/2/4 from this freq. */ clk_dsi_pll = clk_get(&ux500_mcde_device.dev, "dsihs2"); if (DSI_PLL_FREQ_HZ != clk_round_rate(clk_dsi_pll, DSI_PLL_FREQ_HZ)) printk(KERN_ERR "%s: DSI_PLL freq differs %ld\n", __func__, clk_round_rate(clk_dsi_pll, DSI_PLL_FREQ_HZ)); clk_set_rate(clk_dsi_pll, DSI_PLL_FREQ_HZ); clk_put(clk_dsi_pll); /* MCDE pixelfetchwtrmrk levels per overlay */ { #if 1 /* 16 bit overlay */ #define BITS_PER_WORD (4 * 64) u32 fifo = (1024*8 - 8 * BITS_PER_WORD) / 3; fifo &= ~(BITS_PER_WORD - 1); pdata->pixelfetchwtrmrk[0] = fifo * 2 / 32; /* LCD 32bpp */ pdata->pixelfetchwtrmrk[1] = fifo * 1 / 16; /* LCD 16bpp */ #else /* 24 bit overlay */ u32 fifo = (1024*8 - 8 * BITS_PER_WORD) / 7; fifo &= ~(BITS_PER_WORD - 1); pdata->pixelfetchwtrmrk[0] = fifo * 4 / 32; /* LCD 32bpp */ pdata->pixelfetchwtrmrk[1] = fifo * 3 / 24; /* LCD 24bpp */ #endif } pdata->update_opp = update_mcde_opp; ret = mcde_display_device_register(&generic_display0); if (ret) printk(KERN_ERR "Failed to register display device\n"); return ret; }