void bootblock_cpu_init(void) { u32 ret; /* * During Suspend-Resume & S/W-Reset, as soon as PMU releases * pad retention, CKE goes high. This causes memory contents * not to be retained during DRAM initialization. Therfore, * there is a new control register(0x100431e8[28]) which lets us * release pad retention and retain the memory content until the * initialization is complete. */ if (read32(((void *)INF_REG_BASE + INF_REG1_OFFSET)) == S5P_CHECK_SLEEP) { write32(PAD_RETENTION_DRAM_COREBLK_VAL, (void *)PAD_RETENTION_DRAM_COREBLK_OPTION); do { ret = read32((void *)PAD_RETENTION_DRAM_STATUS); } while (ret != 0x1); } /* kick off the multi-core timer. * We want to do this as early as we can. */ mct_start(); if (get_wakeup_state() == WAKEUP_DIRECT) { wakeup(); /* Never returns. */ } /* For most ARM systems, we have to initialize firmware media source * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is * already handled by iROM so there's no need to setup again. */ }
void timer_monotonic_get(struct mono_time *mt) { if (!initialized) { mct_start(); initialized = 1; } mono_time_set_usecs(mt, mct_raw_value() / clocks_per_usec); }
void bootblock_soc_init(void) { /* kick off the multi-core timer. * We want to do this as early as we can. */ mct_start(); if (get_wakeup_state() == WAKEUP_DIRECT) { wakeup(); /* Never returns. */ } /* set up dcache and MMU */ mmu_init(); mmu_disable_range(0, SRAM_START); mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF); dcache_mmu_enable(); /* For most ARM systems, we have to initialize firmware media source * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is * already handled by iROM so there's no need to setup again. */ }