void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output *output, int pipe) { struct drm_device *dev = output->dev; /* clear special packet sent bit */ if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) REG_WRITE(MIPI_INTR_STAT_REG(pipe), DSI_INTR_STATE_SPL_PKG_SENT); /*send turn on package*/ REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_TURN_ON); /*wait for SPL_PKG_SENT interrupt*/ mdfld_wait_for_SPL_PKG_SENT(dev, pipe); if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) REG_WRITE(MIPI_INTR_STAT_REG(pipe), DSI_INTR_STATE_SPL_PKG_SENT); output->panel_on = 1; /* FIXME the following is disabled to WA the X slow start issue for TMD panel if (pipe == 2) dev_priv->dpi_panel_on2 = true; else if (pipe == 0) dev_priv->dpi_panel_on = true; */ }
void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output *output, int pipe) { struct drm_device *dev = output->dev; u32 reg_offset = 0; if(output->panel_on) return; if(pipe) reg_offset = MIPIC_REG_OFFSET; /* clear special packet sent bit */ if(REG_READ(MIPIA_INTR_STAT_REG + reg_offset) & DSI_INTR_STATE_SPL_PKG_SENT) { REG_WRITE((MIPIA_INTR_STAT_REG + reg_offset), DSI_INTR_STATE_SPL_PKG_SENT); } /*send turn on package*/ REG_WRITE((MIPIA_DPI_CONTROL_REG + reg_offset), DSI_DPI_CTRL_HS_TURN_ON); /*wait for SPL_PKG_SENT interrupt*/ mdfld_wait_for_SPL_PKG_SENT(dev, pipe); if(REG_READ(MIPIA_INTR_STAT_REG + reg_offset) & DSI_INTR_STATE_SPL_PKG_SENT) { REG_WRITE((MIPIA_INTR_STAT_REG + reg_offset), DSI_INTR_STATE_SPL_PKG_SENT); } output->panel_on = 1; /* FIXME the following is disabled to WA the X slow start issue for TMD panel */ /* if(pipe == 2) */ /* dev_priv->dpi_panel_on2 = true; */ /* else if (pipe == 0) */ /* dev_priv->dpi_panel_on = true; */ }