int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, int reg, u16 val) { int ret; if (sw_addr == 0) return mdiobus_write(bus, addr, reg, val); /* Wait for the bus to become free. */ ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); if (ret < 0) return ret; /* Transmit the data to write. */ ret = mdiobus_write(bus, sw_addr, 1, val); if (ret < 0) return ret; /* Transmit the write command. */ ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg); if (ret < 0) return ret; /* Wait for the write command to complete. */ ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); if (ret < 0) return ret; return 0; }
static int b53_mdio_op(struct b53_device *dev, u8 page, u8 reg, u16 op) { int i; u16 v; int ret; struct mii_bus *bus = dev->priv; if (dev->current_page != page) { /* set page number */ v = (page << 8) | REG_MII_PAGE_ENABLE; ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_PAGE, v); if (ret) return ret; dev->current_page = page; } /* set register address */ v = (reg << 8) | op; ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_ADDR, v); if (ret) return ret; /* check if operation completed */ for (i = 0; i < 5; ++i) { v = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_ADDR); if (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ))) break; usleep_range(10, 100); } if (WARN_ON(i == 5)) return -EIO; return 0; }
int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, int reg, u16 val) { int ret; if (sw_addr == 0) return mdiobus_write(bus, addr, reg, val); ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); if (ret < 0) return ret; ret = mdiobus_write(bus, sw_addr, 1, val); if (ret < 0) return ret; ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg); if (ret < 0) return ret; ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); if (ret < 0) return ret; return 0; }
static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) { #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0) return mdiobus_write(ds->master_mii_bus, addr, reg, val); #else struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); return mdiobus_write(bus, addr, reg, val); #endif }
static int ip175c_config_init(struct phy_device *phydev) { int err, i; static int full_reset_performed = 0; if (full_reset_performed == 0) { /* master reset */ err = mdiobus_write(phydev->bus, 30, 0, 0x175c); if (err < 0) return err; /* ensure no bus delays overlap reset period */ err = mdiobus_read(phydev->bus, 30, 0); /* data sheet specifies reset period is 2 msec */ mdelay(2); /* enable IP175C mode */ err = mdiobus_write(phydev->bus, 29, 31, 0x175c); if (err < 0) return err; /* Set MII0 speed and duplex (in PHY mode) */ err = mdiobus_write(phydev->bus, 29, 22, 0x420); if (err < 0) return err; /* reset switch ports */ for (i = 0; i < 5; i++) { err = mdiobus_write(phydev->bus, i, MII_BMCR, BMCR_RESET); if (err < 0) return err; } for (i = 0; i < 5; i++) err = mdiobus_read(phydev->bus, i, MII_BMCR); mdelay(2); full_reset_performed = 1; } if (phydev->addr != 4) { phydev->state = PHY_RUNNING; phydev->speed = SPEED_100; phydev->duplex = DUPLEX_FULL; phydev->link = 1; netif_carrier_on(phydev->attached_dev); } return 0; }
int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg) { int ret; if (sw_addr == 0) return mdiobus_read(bus, addr, reg); /* Wait for the bus to become free. */ ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); if (ret < 0) return ret; /* Transmit the read command. */ ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg); if (ret < 0) return ret; /* Wait for the read command to complete. */ ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); if (ret < 0) return ret; /* Read the data. */ ret = mdiobus_read(bus, sw_addr, 1); if (ret < 0) return ret; return ret & 0xffff; }
int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg) { int ret; if (sw_addr == 0) return mdiobus_read(bus, addr, reg); ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); if (ret < 0) return ret; ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg); if (ret < 0) return ret; ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); if (ret < 0) return ret; ret = mdiobus_read(bus, sw_addr, 1); if (ret < 0) return ret; return ret & 0xffff; }
static int b53_mdio_phy_write16(struct b53_device *dev, int addr, u8 reg, u16 value) { struct mii_bus *bus = dev->priv; return mdiobus_write(bus, addr, reg, value); }
static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) { struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); if (bus == NULL) return -EINVAL; return mdiobus_write(bus, ds->pd->sw_addr + addr, reg, val); }
static int b53_mdio_write8(struct b53_device *dev, u8 page, u8 reg, u8 value) { struct mii_bus *bus = dev->priv; int ret; ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0, value); if (ret) return ret; return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); }
static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) { struct bcm_sf2_priv *priv = bus->priv; /* Intercept writes to the Broadcom pseudo-PHY address, else, * send them to our master MDIO bus controller */ if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); else mdiobus_write(priv->master_mii_bus, addr, regnum, val); return 0; }
static int b53_mdio_write64(struct b53_device *dev, u8 page, u8 reg, u64 value) { struct mii_bus *bus = dev->priv; unsigned i; u64 temp = value; for (i = 0; i < 4; i++) { int ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i, temp & 0xffff); if (ret) return ret; temp >>= 16; } return b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE); }
static int xgmiitorgmii_read_status(struct phy_device *phydev) { struct gmii2rgmii *priv = phydev->priv; u16 val = 0; priv->phy_drv->read_status(phydev); val = mdiobus_read(phydev->mdio.bus, priv->addr, XILINX_GMII2RGMII_REG); val &= XILINX_GMII2RGMII_SPEED_MASK; if (phydev->speed == SPEED_1000) val |= BMCR_SPEED1000; else if (phydev->speed == SPEED_100) val |= BMCR_SPEED100; else val |= BMCR_SPEED10; mdiobus_write(phydev->mdio.bus, priv->addr, XILINX_GMII2RGMII_REG, val); return 0; }
static int phylink_phy_write(struct phylink *pl, unsigned int phy_id, unsigned int reg, unsigned int val) { struct phy_device *phydev = pl->phydev; int prtad, devad; if (mdio_phy_id_is_c45(phy_id)) { prtad = mdio_phy_id_prtad(phy_id); devad = mdio_phy_id_devad(phy_id); devad = MII_ADDR_C45 | devad << 16 | reg; } else if (phydev->is_c45) { switch (reg) { case MII_BMCR: case MII_BMSR: case MII_PHYSID1: case MII_PHYSID2: devad = __ffs(phydev->c45_ids.devices_in_package); break; case MII_ADVERTISE: case MII_LPA: if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_AN)) return -EINVAL; devad = MDIO_MMD_AN; if (reg == MII_ADVERTISE) reg = MDIO_AN_ADVERTISE; else reg = MDIO_AN_LPA; break; default: return -EINVAL; } prtad = phy_id; devad = MII_ADDR_C45 | devad << 16 | reg; } else { prtad = phy_id; devad = reg; } return mdiobus_write(phydev->mdio.bus, prtad, devad, val); }
static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) { return mdiobus_write(to_mii_bus(ds->master_dev), ds->pd->sw_addr + addr, reg, val); }
static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) { return mdiobus_write(ds->master_mii_bus, addr, reg, val); }