void mdp3_dma_callback_enable(struct mdp3_dma *dma, int type)
{
int irq_bit;
pr_debug("mdp3_dma_callback_enable type=%d\n", type);
if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_VIDEO ||
dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_LCDC) {
if (type & MDP3_DMA_CALLBACK_TYPE_VSYNC)
mdp3_irq_enable(MDP3_INTR_LCDC_START_OF_FRAME);
} else if (dma->output_config.out_sel == MDP3_DMA_OUTPUT_SEL_DSI_CMD) {
if (type & MDP3_DMA_CALLBACK_TYPE_VSYNC) {
irq_bit = MDP3_INTR_SYNC_PRIMARY_LINE;
irq_bit += dma->dma_sel;
mdp3_irq_enable(irq_bit);
}
if (type & MDP3_DMA_CALLBACK_TYPE_DMA_DONE) {
irq_bit = MDP3_INTR_DMA_P_DONE;
if (dma->dma_sel == MDP3_DMA_S)
irq_bit = MDP3_INTR_DMA_S_DONE;
mdp3_irq_enable(irq_bit);
}
} else {
pr_err("mdp3_dma_callback_enable not supported interface\n");
}
}
static int mdp3_dmap_config(struct mdp3_dma *dma,
struct mdp3_dma_source *source_config,
struct mdp3_dma_output_config *output_config)
{
u32 dma_p_cfg_reg, dma_p_size, dma_p_out_xy;
dma_p_cfg_reg = source_config->format << 25;
if (output_config->dither_en)
dma_p_cfg_reg |= BIT(24);
dma_p_cfg_reg |= output_config->out_sel << 19;
dma_p_cfg_reg |= output_config->bit_mask_polarity << 18;
dma_p_cfg_reg |= output_config->color_components_flip << 14;
dma_p_cfg_reg |= output_config->pack_pattern << 8;
dma_p_cfg_reg |= output_config->pack_align << 7;
dma_p_cfg_reg |= output_config->color_comp_out_bits;
dma_p_size = source_config->width | (source_config->height << 16);
dma_p_out_xy = source_config->x | (source_config->y << 16);
MDP3_REG_WRITE(MDP3_REG_DMA_P_CONFIG, dma_p_cfg_reg);
MDP3_REG_WRITE(MDP3_REG_DMA_P_SIZE, dma_p_size);
MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_ADDR, (u32)source_config->buf);
MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_Y_STRIDE, source_config->stride);
MDP3_REG_WRITE(MDP3_REG_DMA_P_OUT_XY, dma_p_out_xy);
MDP3_REG_WRITE(MDP3_REG_DMA_P_FETCH_CFG, 0x40);
dma->source_config = *source_config;
dma->output_config = *output_config;
mdp3_dma_sync_config(dma, source_config);
mdp3_irq_enable(MDP3_INTR_LCDC_UNDERFLOW);
mdp3_dma_callback_setup(dma);
return 0;
}
static int mdp3_dmap_config(struct mdp3_dma *dma,
struct mdp3_dma_source *source_config,
struct mdp3_dma_output_config *output_config)
{
u32 dma_p_cfg_reg, dma_p_size, dma_p_out_xy;
dma_p_cfg_reg = source_config->format << 25;
if (output_config->dither_en)
dma_p_cfg_reg |= BIT(24);
dma_p_cfg_reg |= output_config->out_sel << 19;
dma_p_cfg_reg |= output_config->bit_mask_polarity << 18;
dma_p_cfg_reg |= output_config->color_components_flip << 14;
dma_p_cfg_reg |= output_config->pack_pattern << 8;
dma_p_cfg_reg |= output_config->pack_align << 7;
dma_p_cfg_reg |= output_config->color_comp_out_bits;
dma_p_size = source_config->width | (source_config->height << 16);
dma_p_out_xy = source_config->x | (source_config->y << 16);
MDP3_REG_WRITE(MDP3_REG_DMA_P_CONFIG, dma_p_cfg_reg);
MDP3_REG_WRITE(MDP3_REG_DMA_P_SIZE, dma_p_size);
MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_ADDR, (u32)source_config->buf);
MDP3_REG_WRITE(MDP3_REG_DMA_P_IBUF_Y_STRIDE, source_config->stride);
MDP3_REG_WRITE(MDP3_REG_DMA_P_OUT_XY, dma_p_out_xy);
/*
* NOTE: MDP_DMA_P_FETCH_CFG: max_burst_size need to use value 4, not
* the default 16 for MDP hang issue workaround
*/
//MDP3_REG_WRITE(MDP3_REG_DMA_P_FETCH_CFG, 0x20);
//to solve the blue flicker of display
MDP3_REG_WRITE(MDP3_REG_DMA_P_FETCH_CFG, 0x40);
MDP3_REG_WRITE(MDP3_REG_PRIMARY_RD_PTR_IRQ, 0x10);
dma->source_config = *source_config;
dma->output_config = *output_config;
mdp3_dma_sync_config(dma, source_config);
mdp3_irq_enable(MDP3_INTR_LCDC_UNDERFLOW);
mdp3_dma_callback_setup(dma);
return 0;
}
