static void mdp4_overlay_dtv_ov_start(struct msm_fb_data_type *mfd) { unsigned long flag; /* enable irq */ if (mfd->ov_start) return; #ifdef CONFIG_MACH_LGE /* QCT Patch : Prevent kernel Crash (mdp4_overlay1_done_dtv()) */ if (!dtv_pipe) { pr_debug("%s: no mixer1 base layer pipe allocated!\n", __func__); return; } #endif if (dtv_pipe->blt_addr) { mdp4_dtv_blt_ov_update(dtv_pipe); dtv_pipe->ov_cnt++; mdp4_overlay_dtv_ov_kick_start(); } spin_lock_irqsave(&mdp_spin_lock, flag); mdp_enable_irq(MDP_OVERLAY1_TERM); INIT_COMPLETION(dtv_pipe->comp); mfd->dma->waiting = TRUE; outp32(MDP_INTR_CLEAR, INTR_OVERLAY1_DONE); mdp_intr_mask |= INTR_OVERLAY1_DONE; outp32(MDP_INTR_ENABLE, mdp_intr_mask); spin_unlock_irqrestore(&mdp_spin_lock, flag); mfd->ov_start = true; }
static void mdp4_overlay_dtv_ov_start(struct msm_fb_data_type *mfd) { unsigned long flag; /* enable irq */ if (mfd->ov_start) return; if (dtv_pipe->blt_addr) { mdp4_dtv_blt_ov_update(dtv_pipe); dtv_pipe->ov_cnt++; mdp4_overlay_dtv_ov_kick_start(); } spin_lock_irqsave(&mdp_spin_lock, flag); mdp_enable_irq(MDP_OVERLAY1_TERM); INIT_COMPLETION(dtv_pipe->comp); mfd->dma->waiting = TRUE; outp32(MDP_INTR_CLEAR, INTR_OVERLAY1_DONE); mdp_intr_mask |= INTR_OVERLAY1_DONE; outp32(MDP_INTR_ENABLE, mdp_intr_mask); spin_unlock_irqrestore(&mdp_spin_lock, flag); mfd->ov_start = true; }