static int edp_event_thread(void *data)
{
struct mdss_edp_drv_pdata *ep;
unsigned long flag;
u32 todo = 0;
ep = (struct mdss_edp_drv_pdata *)data;
while (1) {
if (wait_event_interruptible(ep->event_q,
(ep->event_pndx != ep->event_gndx)) != 0)
continue;
spin_lock_irqsave(&ep->event_lock, flag);
if (ep->event_pndx == ep->event_gndx) {
spin_unlock_irqrestore(&ep->event_lock, flag);
break;
}
todo = ep->event_todo_list[ep->event_gndx];
ep->event_todo_list[ep->event_gndx++] = 0;
ep->event_gndx %= HPD_EVENT_MAX;
spin_unlock_irqrestore(&ep->event_lock, flag);
pr_debug("%s: todo=%x\n", __func__, todo);
if (todo == 0)
continue;
if (todo & EV_EDID_READ)
mdss_edp_edid_read(ep, 0);
if (todo & EV_DPCD_CAP_READ)
mdss_edp_dpcd_cap_read(ep);
if (todo & EV_DPCD_STATUS_READ)
mdss_edp_dpcd_status_read(ep);
if (todo & EV_LINK_TRAIN)
mdss_edp_do_link_train(ep);
if (todo & EV_VIDEO_READY)
mdss_edp_video_ready(ep);
if (todo & EV_IDLE_PATTERNS_SENT)
mdss_edp_idle_patterns_sent(ep);
}
return 0;
}
int edp_prepare(void)
{
mdss_edp_aux_init();
edp_phy_pll_reset();
edp_mainlink_reset();
edp_aux_reset();
edp_phy_powerup(1);
edp_aux_enable();
mdss_edp_irq_enable();
mdss_edp_wait_for_hpd();
mdss_edp_edid_read();
mdss_edp_dpcd_cap_read();
edp_edid2pinfo(edp_pinfo);
edp_cap2pinfo(edp_pinfo);
dprintf(INFO, "%s:\n", __func__);
return 0;
}
static int mdss_edp_probe(struct platform_device *pdev)
{
int ret;
struct mdss_edp_drv_pdata *edp_drv;
struct mdss_panel_cfg *pan_cfg = NULL;
if (!mdss_is_ready()) {
pr_err("%s: MDP not probed yet!\n", __func__);
return -EPROBE_DEFER;
}
pan_cfg = mdss_panel_intf_type(MDSS_PANEL_INTF_EDP);
if (IS_ERR(pan_cfg)) {
return PTR_ERR(pan_cfg);
} else if (!pan_cfg) {
pr_debug("%s: not configured as prim\n", __func__);
return -ENODEV;
}
if (!pdev->dev.of_node) {
pr_err("%s: Failed\n", __func__);
return -EPERM;
}
edp_drv = devm_kzalloc(&pdev->dev, sizeof(*edp_drv), GFP_KERNEL);
if (edp_drv == NULL) {
pr_err("%s: Failed, could not allocate edp_drv", __func__);
return -ENOMEM;
}
edp_drv->mdss_util = mdss_get_util_intf();
if (edp_drv->mdss_util == NULL) {
pr_err("Failed to get mdss utility functions\n");
return -ENODEV;
}
edp_drv->panel_data.panel_info.is_prim_panel = true;
mdss_edp_hw.irq_info = mdss_intr_line();
if (mdss_edp_hw.irq_info == NULL) {
pr_err("Failed to get mdss irq information\n");
return -ENODEV;
}
edp_drv->pdev = pdev;
edp_drv->pdev->id = 1;
edp_drv->clk_on = 0;
edp_drv->aux_rate = 19200000;
edp_drv->mask1 = EDP_INTR_MASK1;
edp_drv->mask2 = EDP_INTR_MASK2;
mutex_init(&edp_drv->emutex);
spin_lock_init(&edp_drv->lock);
ret = mdss_edp_get_base_address(edp_drv);
if (ret)
goto probe_err;
ret = mdss_edp_get_mmss_cc_base_address(edp_drv);
if (ret)
goto edp_base_unmap;
ret = mdss_edp_regulator_init(edp_drv);
if (ret)
goto mmss_cc_base_unmap;
ret = mdss_edp_clk_init(edp_drv);
if (ret)
goto edp_clk_deinit;
ret = mdss_edp_gpio_panel_en(edp_drv);
if (ret)
goto edp_clk_deinit;
ret = mdss_edp_gpio_lvl_en(edp_drv);
if (ret)
pr_err("%s: No gpio_lvl_en detected\n", __func__);
ret = mdss_edp_pwm_config(edp_drv);
if (ret)
goto edp_free_gpio_panel_en;
mdss_edp_irq_setup(edp_drv);
mdss_edp_aux_init(edp_drv);
mdss_edp_event_setup(edp_drv);
edp_drv->cont_splash = of_property_read_bool(pdev->dev.of_node,
"qcom,cont-splash-enabled");
/* only need aux and ahb clock for aux channel */
mdss_edp_prepare_aux_clocks(edp_drv);
mdss_edp_aux_clk_enable(edp_drv);
if (!edp_drv->cont_splash) {
mdss_edp_phy_pll_reset(edp_drv);
mdss_edp_aux_reset(edp_drv);
mdss_edp_mainlink_reset(edp_drv);
mdss_edp_phy_power_ctrl(edp_drv, 1);
mdss_edp_aux_ctrl(edp_drv, 1);
}
mdss_edp_irq_enable(edp_drv);
mdss_edp_edid_read(edp_drv, 0);
mdss_edp_dpcd_cap_read(edp_drv);
mdss_edp_fill_link_cfg(edp_drv);
mdss_edp_irq_disable(edp_drv);
if (!edp_drv->cont_splash) {
mdss_edp_aux_ctrl(edp_drv, 0);
mdss_edp_phy_power_ctrl(edp_drv, 0);
}
mdss_edp_aux_clk_disable(edp_drv);
mdss_edp_unprepare_aux_clocks(edp_drv);
if (edp_drv->cont_splash) { /* vote for clocks */
mdss_edp_prepare_clocks(edp_drv);
mdss_edp_clk_enable(edp_drv);
}
mdss_edp_device_register(edp_drv);
edp_drv->inited = true;
pr_debug("%s: done\n", __func__);
return 0;
edp_free_gpio_panel_en:
gpio_free(edp_drv->gpio_panel_en);
if (gpio_is_valid(edp_drv->gpio_lvl_en))
gpio_free(edp_drv->gpio_lvl_en);
edp_clk_deinit:
mdss_edp_clk_deinit(edp_drv);
mdss_edp_regulator_off(edp_drv);
mmss_cc_base_unmap:
iounmap(edp_drv->mmss_cc_base);
edp_base_unmap:
iounmap(edp_drv->base);
probe_err:
return ret;
}
static int __devinit mdss_edp_probe(struct platform_device *pdev)
{
int ret;
struct mdss_edp_drv_pdata *edp_drv;
struct mdss_panel_cfg *pan_cfg = NULL;
if (!mdss_is_ready()) {
pr_err("%s: MDP not probed yet!\n", __func__);
return -EPROBE_DEFER;
}
pan_cfg = mdss_panel_intf_type(MDSS_PANEL_INTF_EDP);
if (IS_ERR(pan_cfg)) {
return PTR_ERR(pan_cfg);
} else if (!pan_cfg) {
pr_debug("%s: not configured as prim\n", __func__);
return -ENODEV;
}
if (!pdev->dev.of_node) {
pr_err("%s: Failed\n", __func__);
return -EPERM;
}
edp_drv = devm_kzalloc(&pdev->dev, sizeof(*edp_drv), GFP_KERNEL);
if (edp_drv == NULL) {
pr_err("%s: Failed, could not allocate edp_drv", __func__);
return -ENOMEM;
}
edp_drv->pdev = pdev;
edp_drv->pdev->id = 1;
edp_drv->clk_on = 0;
edp_drv->train_start = 0; /* no link train yet */
ret = mdss_edp_get_base_address(edp_drv);
if (ret)
goto probe_err;
ret = mdss_edp_get_mmss_cc_base_address(edp_drv);
if (ret)
goto edp_base_unmap;
ret = mdss_edp_regulator_init(edp_drv);
if (ret)
goto mmss_cc_base_unmap;
ret = mdss_edp_clk_init(edp_drv);
if (ret)
goto edp_clk_deinit;
ret = mdss_edp_gpio_panel_en(edp_drv);
if (ret)
goto edp_clk_deinit;
ret = mdss_edp_pwm_config(edp_drv);
if (ret)
goto edp_free_gpio_panel_en;
mdss_edp_irq_setup(edp_drv);
mdss_edp_aux_init(edp_drv);
mdss_edp_event_setup(edp_drv);
/* need mdss clock to receive irq */
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
/* only need aux and ahb clock for aux channel */
mdss_edp_prepare_aux_clocks(edp_drv);
mdss_edp_aux_clk_enable(edp_drv);
mdss_edp_phy_pll_reset(edp_drv->base);
mdss_edp_aux_reset(edp_drv->base);
mdss_edp_mainlink_reset(edp_drv->base);
mdss_edp_phy_powerup(edp_drv->base, 1);
mdss_edp_aux_ctrl(edp_drv->base, 1);
mdss_edp_irq_enable(edp_drv);
mdss_edp_edid_read(edp_drv, 0);
mdss_edp_dpcd_cap_read(edp_drv);
mdss_edp_irq_disable(edp_drv);
mdss_edp_aux_ctrl(edp_drv->base, 0);
mdss_edp_aux_clk_disable(edp_drv);
mdss_edp_phy_powerup(edp_drv->base, 0);
mdss_edp_unprepare_aux_clocks(edp_drv);
mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
mdss_edp_device_register(edp_drv);
return 0;
edp_free_gpio_panel_en:
gpio_free(edp_drv->gpio_panel_en);
edp_clk_deinit:
mdss_edp_clk_deinit(edp_drv);
mdss_edp_regulator_off(edp_drv);
mmss_cc_base_unmap:
iounmap(edp_drv->mmss_cc_base);
edp_base_unmap:
iounmap(edp_drv->base);
probe_err:
return ret;
}