static int mdss_mdp_ctl_perf_update(struct mdss_mdp_ctl *ctl) { int ret = MDSS_MDP_PERF_UPDATE_SKIP; u32 clk_rate, ab_quota, ib_quota; u32 max_clk_rate = 0, total_ab_quota = 0, total_ib_quota = 0; if (ctl->mixer_left) { mdss_mdp_perf_mixer_update(ctl->mixer_left, &ab_quota, &ib_quota, &clk_rate); total_ab_quota += ab_quota; total_ib_quota += ib_quota; max_clk_rate = clk_rate; } if (ctl->mixer_right) { mdss_mdp_perf_mixer_update(ctl->mixer_right, &ab_quota, &ib_quota, &clk_rate); total_ab_quota += ab_quota; total_ib_quota += ib_quota; if (clk_rate > max_clk_rate) max_clk_rate = clk_rate; if (ctl->intf_type) { clk_rate = mdss_mdp_get_pclk_rate(ctl); /* minimum clock rate due to inefficiency in 3dmux */ clk_rate = mult_frac(clk_rate >> 1, 9, 8); if (clk_rate > max_clk_rate) max_clk_rate = clk_rate; }
static int mdss_mdp_ctl_perf_update(struct mdss_mdp_ctl *ctl, u32 *flags) { int ret = MDSS_MDP_PERF_UPDATE_SKIP; u32 clk_rate, ab_quota, ib_quota; u32 max_clk_rate = 0, total_ab_quota = 0, total_ib_quota = 0; if (ctl->mixer_left) { mdss_mdp_perf_mixer_update(ctl->mixer_left, &ab_quota, &ib_quota, &clk_rate); total_ab_quota += ab_quota; total_ib_quota += ib_quota; max_clk_rate = clk_rate; } if (ctl->mixer_right) { mdss_mdp_perf_mixer_update(ctl->mixer_right, &ab_quota, &ib_quota, &clk_rate); total_ab_quota += ab_quota; total_ib_quota += ib_quota; if (clk_rate > max_clk_rate) max_clk_rate = clk_rate; } *flags = 0; if (max_clk_rate != ctl->clk_rate) { if (max_clk_rate > ctl->clk_rate) ret = MDSS_MDP_PERF_UPDATE_EARLY; else ret = MDSS_MDP_PERF_UPDATE_LATE; ctl->clk_rate = max_clk_rate; *flags |= MDSS_MDP_PERF_UPDATE_CLK; } if ((total_ab_quota != ctl->bus_ab_quota) || (total_ib_quota != ctl->bus_ib_quota)) { if (ret == MDSS_MDP_PERF_UPDATE_SKIP) { if (total_ib_quota > ctl->bus_ib_quota) ret = MDSS_MDP_PERF_UPDATE_EARLY; else ret = MDSS_MDP_PERF_UPDATE_LATE; } ctl->bus_ab_quota = total_ab_quota; ctl->bus_ib_quota = total_ib_quota; *flags |= MDSS_MDP_PERF_UPDATE_BUS; } return ret; }