static int mem_gets(BIO *bio, char *buf, int size) { int i, j; char *p; BUF_MEM *b = (BUF_MEM *)bio->ptr; BIO_clear_retry_flags(bio); j = b->length; if (size - 1 < j) { j = size - 1; } if (j <= 0) { if (size > 0) { *buf = 0; } return 0; } p = b->data; for (i = 0; i < j; i++) { if (p[i] == '\n') { i++; break; } } /* i is now the max num of bytes to copy, either j or up to and including the * first newline */ i = mem_read(bio, buf, i); if (i > 0) { buf[i] = '\0'; } return i; }
/* ------------------------------------------------------------------------*//** * @FUNCTION clk_am335x_sysclk_rate_get * @BRIEF Return the mandatory system clock speed, in MHz. * @RETURNS > 0 system clock speed, in MHz. * OMAPCONF_ERR_CPU * OMAPCONF_ERR_UNEXPECTED * @param[in] none * @DESCRIPTION Return the mandatory system clock speed, in MHz. *//*------------------------------------------------------------------------ */ double clk_am335x_sysclk_rate_get(void) { unsigned int reg_val; static double sysclk = 0.0; sysclk_am335x_id sysclk_id; if (!cpu_is_am335x()) return (double) OMAPCONF_ERR_CPU; if (sysclk > 0.0) { dprintf("%s(): sysclk rate=%.1lfMHz\n", __func__, sysclk); return sysclk; } if (!mem_fake_access_get()) { mem_read(AM335X_STATUS, ®_val); sysclk_id = extract_bitfield(reg_val, 22, 2); } else { sysclk_id = SYSCLK_AM335X_19_2_MHZ; /* AM335X EVM PoR */ } sysclk = sysclk_am335x_rate_table[sysclk_id]; if (sysclk == 0.0) { fprintf(stderr, "%s(): bad CONTROL_STATUS value(%d)\n", __func__, sysclk_id); sysclk = (double) OMAPCONF_ERR_UNEXPECTED; } else { dprintf("%s(): CONTROL_STATUS=0x%x, sysclk rate=%.1lfMHz\n", __func__, sysclk_id, sysclk); } return sysclk; }
/* * memoryStage - writes or reads from memory when needed * Updates values for writebackStage * * params - forwardType * forward, statusType* status, bubbleType* bubble * */ void memoryStage(forwardType * forward, statusType* status, bubbleType* bubble) { unsigned int addr = mem_addr(); unsigned int valM = M.valA; bool memError = false; unsigned int stat = M.stat; if(mem_write()) { putWord(addr, valM, &memError); } if(mem_read()) { valM = getWord(addr, &memError); } if(memError) stat = SADR; //forward values forward->M_dstM = M.dstM; forward->M_dstE = M.dstE; forward->m_valM = valM; forward->M_valE = M.valE; forward->M_Cnd = M.Cnd; forward->M_valA = M.valA; forward->M_icode = M.icode; status->m_stat = stat; bubble->M_icode = M.icode; updateWregister(stat, M.icode, M.valE, valM, M.dstE, M.dstM); }
/* ------------------------------------------------------------------------*//** * @FUNCTION stm_atb_capture_disable * @BRIEF disable STM trace capture in ETB via ATB * @RETURNS 0 in case of success * OMAPCONF_ERR_NOT_AVAILABLE * @DESCRIPTION disable STM trace capture in ETB via ATB * NB: make sure EMU domain is ON before calling this * function. * NB: blocking until STM FIFO is empty *//*------------------------------------------------------------------------ */ int stm_atb_capture_disable(void) { unsigned int stm_sysstatus; if (!emu44xx_is_enabled()) { printf("stm_atb_capture_disable(): EMU domain OFF!!!\n"); return OMAPCONF_ERR_NOT_AVAILABLE; } if (!stm_is_claimed()) { printf("stm_atb_capture_disable(): STM not claimed!\n"); return OMAPCONF_ERR_INTERNAL; } do { mem_read(OMAP4430_STM_SYSSTATUS, &stm_sysstatus); } while (stm_sysstatus != 0x00000101); dprintf("stm_atb_capture_disable(): STM FIFO empty.\n"); /* Disable ATB */ mem_write(OMAP4430_ATB_CONFIG, 0x00000000); dprintf("stm_atb_capture_disable(): ATB capture disabled.\n"); #ifdef STM_OMAP4_DEBUG stm_last_header_pos_get(); stm_dump_regs(); #endif return 0; }
static int identify_am335x_features(void) { unsigned int dev_feat; if (mem_read(AM335X_DEV_FEAT_REG, &dev_feat) != 0) return OMAPCONF_ERR_REG_ACCESS; switch (dev_feat) { case AM3352_DEV_FEAT: cpu_set(AM_3352); break; case AM3354_DEV_FEAT: cpu_set(AM_3354); break; case AM3356_DEV_FEAT: cpu_set(AM_3356); break; case AM3357_DEV_FEAT: cpu_set(AM_3357); break; case AM3358_DEV_FEAT: cpu_set(AM_3358); break; case AM3359_DEV_FEAT: cpu_set(AM_3359); break; default: cpu_set(AM_335X); break; } return 0; }
void mips_isa_LBU_impl(struct mips_ctx_t *ctx) { unsigned char temp; unsigned int addr = mips_gpr_get_value(ctx, RS) + SEXT32(IMM, 16); mem_read(ctx->mem, addr, sizeof(unsigned char), &temp); mips_gpr_set_value(ctx, RT, (unsigned)temp); mips_isa_inst_debug(" r%d=0x%x", RT, mips_gpr_get_value(ctx, RT)); }
void dp8390_device::do_tx() { UINT8 *buf; int i; UINT32 high16 = (m_regs.dcr & 4)?m_regs.rsar<<16:0; if(m_reset) return; if(LOOPBACK) return; // TODO: loopback m_regs.tsr = 0; if(m_regs.tbcr > 1518) logerror("dp8390: trying to send overlong frame\n"); if(!m_regs.tbcr) { // ? Bochs says solaris actually does this m_regs.tsr = 1; m_regs.cr &= ~4; return; } buf = global_alloc_array(UINT8, m_regs.tbcr); for(i = 0; i < m_regs.tbcr; i++) buf[i] = mem_read(high16 + (m_regs.tpsr << 8) + i); if(send(buf, m_regs.tbcr)) { m_regs.tsr = 1; m_regs.isr |= 2; } else { m_regs.tsr = 8; // not quite right but there isn't a generic "tx failed" m_regs.isr |= 8; } m_regs.cr &= ~4; check_irq(); global_free(buf); }
static int mem_gets(BIO *bp, char *buf, int size) { int i,j; int ret= -1; char *p; BUF_MEM *bm=(BUF_MEM *)bp->ptr; BIO_clear_retry_flags(bp); j=bm->length; if (j <= 0) { *buf='\0'; return 0; } p=bm->data; for (i=0; i<j; i++) { if (p[i] == '\n') break; } if (i == j) { BIO_set_retry_read(bp); /* return(-1); change the semantics 0.6.6a */ } else i++; /* i is the max to copy */ if ((size-1) < i) i=size-1; i=mem_read(bp,buf,i); if (i > 0) buf[i]='\0'; ret=i; return(ret); }
/* ------------------------------------------------------------------------*//** * @FUNCTION sr44xx_is_enabled * @BRIEF Check if SR module is enabled * @RETURNS 1 if module is enabled, 0 otherwise * @param[in] sr_id: SR module ID * @DESCRIPTION Check if SR module is enabled *//*------------------------------------------------------------------------ */ unsigned int sr44xx_is_enabled(omap4_sr_module_id sr_id) { unsigned int sr_config_addr, sr_config; mod44xx_id module_id; int ret; switch (sr_id) { case OMAP4_SR_MPU: sr_config_addr = OMAP4430_SR_MPU_SRCONFIG; module_id = OMAP4_SMARTREFLEX_MPU; break; case OMAP4_SR_IVA: sr_config_addr = OMAP4430_SR_IVA_SRCONFIG; module_id = OMAP4_SMARTREFLEX_IVA; break; case OMAP4_SR_CORE: sr_config_addr = OMAP4430_SR_CORE_SRCONFIG; module_id = OMAP4_SMARTREFLEX_CORE; break; default: return 0; } /* Read SR_CONFIG register (if accessible) */ if (mod44xx_is_accessible(module_id) != 1) return 0; ret = mem_read(sr_config_addr, &sr_config); if (ret != 0) return 0; return sr_is_enabled(sr_config); }
void si_ndrange_const_buf_write(struct si_ndrange_t *ndrange, int const_buf_num, int offset, void *pvalue, unsigned int size) { unsigned int addr; struct si_buffer_desc_t buffer_desc; /* Sanity check */ assert(const_buf_num < 2); if (const_buf_num == 0) { assert(offset + size < SI_EMU_CONST_BUF_0_SIZE); } else if (const_buf_num == 1) { assert(offset + size < SI_EMU_CONST_BUF_1_SIZE); } mem_read(si_emu->global_mem, ndrange->const_buf_table + const_buf_num*SI_EMU_CONST_BUF_TABLE_ENTRY_SIZE, sizeof(buffer_desc), &buffer_desc); addr = (unsigned int)buffer_desc.base_addr; addr += offset; /* Write */ mem_write(si_emu->global_mem, addr, size, pvalue); }
/* ------------------------------------------------------------------------*//** * @FUNCTION stm_hw_master_disable * @BRIEF disable stm hw master * @RETURNS 0 in case of success * OMAPCONF_ERR_NOT_AVAILABLE * OMAPCONF_ERR_INTERNAL * OMAPCONF_ERR_ARG * @param[in] pos: register position * @DESCRIPTION disable stm hw master *//*------------------------------------------------------------------------ */ int stm_hw_master_disable(unsigned char pos) { unsigned int stm_hwmctrl, mask; if (!emu44xx_is_enabled()) { printf("stm_hw_master_disable(): " "trying to enable ETB but EMU domain OFF!!!\n"); return OMAPCONF_ERR_NOT_AVAILABLE; } if (!stm_is_claimed()) { printf("stm_hw_master_disable(): STM not claimed!\n"); return OMAPCONF_ERR_INTERNAL; } if (pos > 3) { printf("stm_hw_master_disable(): pos (%d) > 3!\n", pos); return OMAPCONF_ERR_ARG; } mem_read(OMAP4430_STM_HWMCTRL, &stm_hwmctrl); pos = 2 + (8 * pos); mask = ~(0x1F << pos); stm_hwmctrl &= mask; mem_write(OMAP4430_STM_HWMCTRL, stm_hwmctrl); return 0; }
static int disasm_read_memory(bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, struct disassemble_info *info){ int ret; int i; for(i = 0; i < length; i++) ret = mem_read(8, memaddr + i, (myaddr + i)); return 0; }
void mips_isa_LL_impl(struct mips_ctx_t *ctx) { unsigned int temp; mem_read(ctx->mem, mips_gpr_get_value(ctx,RS) + IMM, sizeof(unsigned int), &temp); mips_gpr_set_value(ctx,RT, temp); // FIXME: add details from m2s-1.3/src/kernel/machine.def }
void mips_isa_LHU_impl(struct mips_ctx_t *ctx) { unsigned short int temp; unsigned int addr = mips_gpr_get_value(ctx,RS) + IMM; mem_read(ctx->mem, addr, sizeof(unsigned short int), &temp); mips_gpr_set_value(ctx,RT, temp); }
/* put character into the keyboard queue inside the emulation */ static void tokbdbuffer(int c) { int num = mem_read((uint16_t)(num_pending_location)); /* printf("tokbdbuffer c:%d num:%d\n", c, num); */ mem_inject((uint16_t)(buffer_location + num), (uint8_t)c); mem_inject((uint16_t)(num_pending_location), (uint8_t)(num + 1)); }
void mips_isa_LB_impl(struct mips_ctx_t *ctx) { unsigned char temp; unsigned int addr = mips_gpr_get_value(ctx,RS) + SEXT32(IMM,16); mem_read(ctx->mem, addr, sizeof(unsigned char), &temp); mips_gpr_set_value(ctx,RT, SEXT32(temp, 8)); }
static int mem_gets(BIO *bp, char *buf, int size) { int i, j; int ret = -1; char *p; BUF_MEM *bm = (BUF_MEM *)bp->ptr; BIO_clear_retry_flags(bp); j = bm->length; if ((size - 1) < j) j = size - 1; if (j <= 0) { *buf = '\0'; return 0; } p = bm->data; for (i = 0; i < j; i++) { if (p[i] == '\n') { i++; break; } } /* * i is now the max num of bytes to copy, either j or up to * and including the first newline */ i = mem_read(bp, buf, i); if (i > 0) buf[i] = '\0'; ret = i; return (ret); }
/* ------------------------------------------------------------------------*//** * @FUNCTION coresight_etb_buffer_read * @BRIEF read ETB RAM buffer data at given position * @RETURNS 0 in case of success * OMAPCONF_ERR_ARG in case of error * @param[in] rrp: read pointer (position in buffer from 0 * to OMAP44xx_ETB_RAM_SIZE/4) * @param[in,out] rrd: data read from ETB buffer at position 'rrp' * @DESCRIPTION read ETB RAM buffer data at given position *//*------------------------------------------------------------------------ */ int coresight_etb_buffer_read(unsigned int rrp, unsigned int *rrd) { if (rrp >= (OMAP44xx_ETB_RAM_SIZE / 4)) { fprintf(stderr, "coresight_etb_buffer_read(): " "rrp (%d) >= OMAP44xx_ETB_RAM_SIZE / 4 (%d)!\n", rrp, OMAP44xx_ETB_RAM_SIZE / 4); return OMAPCONF_ERR_ARG; } if (rrd == NULL) { fprintf(stderr, "coresight_etb_buffer_read(): rrd == NULL!\n"); return OMAPCONF_ERR_ARG; } /* Set read pointer */ mem_write(OMAP4430_ETB_RRP, rrp); /* Read data in ETB at location pointed by rrp */ #ifdef CORESIGHT_ETB_SAVE_TRACE_DEBUG *rrd = rrp; #else mem_read(OMAP4430_ETB_RRD, rrd); #endif return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION emu44xx_dependency_show * @BRIEF analyse dependency configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyse dependency configuration *//*------------------------------------------------------------------------ */ int emu44xx_dependency_show(FILE *stream) { unsigned int cm_dynamicdep; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) emu44xx_regtable_init(); if (mem_read(OMAP4430_CM_EMU_DYNAMICDEP, &cm_dynamicdep) != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("OMAP4430_CM_EMU_DYNAMICDEP = 0x%08X\n", cm_dynamicdep); fprintf(stream, "|--------------------------------------------------------|\n"); fprintf(stream, "| EMU Domain Dependency Configuration | Static | Dynamic |\n"); fprintf(stream, "|-------------------------------------|------------------|\n"); fprintf(stream, "| %-35s | %-6s | %-7s |\n", "L3_2", "", ((extract_bit(cm_dynamicdep, 6) == 1) ? "En" : "Dis")); fprintf(stream, "|--------------------------------------------------------|\n"); fprintf(stream, "| %-44s | %-7d |\n", "Window Size", extract_bitfield(cm_dynamicdep, 24, 4)); fprintf(stream, "|--------------------------------------------------------|\n"); fprintf(stream, "\n"); return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION stm_last_header_pos_get * @BRIEF return the position of the last STP header in the last * 32-bit ATB word stored * @RETURNS >=0 STP header position * <8 STP header is in the last ETB entry * >=8 STP header is in the (last -1) ETB entry * OMAPCONF_ERR_NOT_AVAILABLE * OMAPCONF_ERR_INTERNAL * @DESCRIPTION return the position of the last STP header in the last * 32-bit ATB word stored * NB: make sure EMU domain is ON before calling this * function. *//*------------------------------------------------------------------------ */ int stm_last_header_pos_get(void) { unsigned int atb_pointer; if (!emu44xx_is_enabled()) { printf("stm_atb_capture_disable(): " "trying to enable ETB but EMU domain OFF!!!\n"); return OMAPCONF_ERR_INTERNAL; } if (!stm_is_claimed()) { printf("stm_atb_capture_disable(): STM not claimed!\n"); return OMAPCONF_ERR_INTERNAL; } mem_read(OMAP4430_ATB_POINTER, &atb_pointer); dprintf("stm_last_header_pos_get(): atb_pointer = 0x%08X\n", atb_pointer); if ((atb_pointer & 0x00000008) == 0x00000008) { dprintf("stm_last_header_pos_get(): " "STP Header pos = %d in last ETB entry\n", atb_pointer & 0x00000007); return (atb_pointer & 0x00000007); } else if ((atb_pointer & 0x00000080) == 0x00000080) { dprintf("stm_last_header_pos_get(): " "STP Header pos = %d in (last -1) ETB entry\n", 8 + ((atb_pointer & 0x00000070) >> 4)); return (8 + ((atb_pointer & 0x00000070) >> 4)); } else {
/* ------------------------------------------------------------------------*//** * @FUNCTION dsp44xx_config_show * @BRIEF analyze DSP power configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyze DSP power configuration *//*------------------------------------------------------------------------ */ int dsp44xx_config_show(FILE *stream) { unsigned int pm_pwstctrl; unsigned int pm_pwstst; unsigned int cm_clkstctrl; unsigned int rm_context; unsigned int cm_clkctrl; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) dsp44xx_regtable_init(); if (mem_read(OMAP4430_CM_DSP_DSP_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_DSP_DSP_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; /* Power Domain Configuration */ if (mem_read(OMAP4430_PM_DSP_PWRSTCTRL, &pm_pwstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_DSP_PWRSTST, &pm_pwstst) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = pwrdm44xx_config_show(stream, "DSP", OMAP4430_PM_DSP_PWRSTCTRL, pm_pwstctrl, OMAP4430_PM_DSP_PWRSTST, pm_pwstst); if (ret != 0) return ret; /* Clock Domain Configuration */ if (mem_read(OMAP4430_CM_DSP_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = clkdm44xx_config_show(stream, "DSP", OMAP4430_CM_DSP_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; /* Module Power Configuration */ ret = mod44xx_config_show(stream, "DSP", OMAP4430_CM_DSP_DSP_CLKCTRL, cm_clkctrl, OMAP4430_RM_DSP_DSP_CONTEXT, rm_context); if (ret != 0) return ret; return 0; }
void mips_isa_LWC1_impl(struct mips_ctx_t *ctx) { unsigned int temp; float f; mem_read(ctx->mem, mips_gpr_get_value(ctx,RS) + IMM, sizeof(unsigned int), &temp); f = *(float *) &temp; MIPS_FPR_S_SET(FT, f); }
JNIEXPORT jstring JNICALL Java_go_Seq_readUTF16(JNIEnv *env, jobject obj) { int32_t size = *MEM_READ(obj, int32_t); if (size == 0) { return NULL; } return (*env)->NewString(env, (jchar*)mem_read(env, obj, 2*size, 1), size); }
void mem_read(Stream & mem, DDSPixelFormat & pf) { mem_read(mem, pf.size); mem_read(mem, pf.flags); mem_read(mem, pf.fourcc); mem_read(mem, pf.bitcount); mem_read(mem, pf.rmask); mem_read(mem, pf.gmask); mem_read(mem, pf.bmask); mem_read(mem, pf.amask); }
/* ------------------------------------------------------------------------*//** * @FUNCTION coresight_etb_buffer_overflow * @BRIEF check if ETB RAM buffer overflow occurred * @RETURNS 0 if no overflow occurred * 1 if overflow occurred * @DESCRIPTION check if ETB RAM buffer overflow occurred *//*------------------------------------------------------------------------ */ int coresight_etb_buffer_overflow(void) { unsigned int sts; /* Check if RAM write pointer has wrapped around */ mem_read(OMAP4430_ETB_STS, &sts); return (sts & 0x00000001); }
void core_fetch(void) { if (! running) { logmsg(LOG_WARN, "Core: maschine is not running. Can not fetch."); return; } mem_read(instruction, registers[PC].value, 4); }
void mips_isa_LWR_impl(struct mips_ctx_t *ctx) { unsigned char src[4]; unsigned int rt_value = mips_gpr_get_value(ctx, RT); unsigned char *dst = (unsigned char *)&rt_value; unsigned int addr = mips_gpr_get_value(ctx, RS) + SEXT32(IMM, 16); int i, size = 1 + (addr & 3); mem_read(ctx->mem, addr - size + 1, size, src); for (i = 0; i < size; i++) dst[size - i - 1] = src[i]; }
void frm_isa_const_mem_read(unsigned int addr, void *pvalue) { /* Warn if c[0][0..1c] is used uninitialized */ if (addr < 0x20 && !frm_emu->const_mem_init[addr]) warning("c [0] [0x%x] is used uninitialized", addr); /* Read */ mem_read(frm_emu->const_mem, addr, sizeof(unsigned int), pvalue); }
/* ------------------------------------------------------------------------*//** * @FUNCTION emu44xx_config_show * @BRIEF analyze power configuration * @RETURNS 0 in case of success * OMAPCONF_ERR_CPU * OMAPCONF_ERR_REG_ACCESS * @param[in] stream: output file stream * @DESCRIPTION analyze power configuration *//*------------------------------------------------------------------------ */ int emu44xx_config_show(FILE *stream) { unsigned int pm_pwstctrl; unsigned int pm_pwstst; unsigned int cm_clkstctrl; unsigned int rm_context; unsigned int cm_clkctrl; int ret; CHECK_CPU(44xx, OMAPCONF_ERR_CPU); if (!init_done) emu44xx_regtable_init(); if (mem_read(OMAP4430_PM_EMU_PWRSTCTRL, &pm_pwstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_PM_EMU_PWRSTST, &pm_pwstst) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_CM_EMU_CLKSTCTRL, &cm_clkstctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = pwrdm44xx_config_show(stream, "EMU", OMAP4430_PM_EMU_PWRSTCTRL, pm_pwstctrl, OMAP4430_PM_EMU_PWRSTST, pm_pwstst); if (ret != 0) return ret; ret = clkdm44xx_config_show(stream, "EMU", OMAP4430_CM_EMU_CLKSTCTRL, cm_clkstctrl); if (ret != 0) return ret; if (mem_read(OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, &cm_clkctrl) != 0) return OMAPCONF_ERR_REG_ACCESS; if (mem_read(OMAP4430_RM_EMU_DEBUGSS_CONTEXT, &rm_context) != 0) return OMAPCONF_ERR_REG_ACCESS; ret = mod44xx_config_show(stream, "DEBUGSS", OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, cm_clkctrl, OMAP4430_RM_EMU_DEBUGSS_CONTEXT, rm_context); return ret; }
int bmlipc_read_int (BmlIpcBuf * self) { int buffer = 0; if (mem_read (self, &buffer, sizeof (buffer), 1) != 1) { self->io_error = 1; } return buffer; }