static void nrf51_nvm_realize(DeviceState *dev, Error **errp) { NRF51NVMState *s = NRF51_NVM(dev); Error *err = NULL; memory_region_init_rom_device(&s->flash, OBJECT(dev), &flash_ops, s, "nrf51_soc.flash", s->flash_size, &err); if (err) { error_propagate(errp, err); return; } s->storage = memory_region_get_ram_ptr(&s->flash); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->flash); }
static void boston_mach_init(MachineState *machine) { DeviceState *dev; BostonState *s; Error *err = NULL; const char *cpu_model; MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg; MemoryRegion *sys_mem = get_system_memory(); XilinxPCIEHost *pcie2; PCIDevice *ahci; DriveInfo *hd[6]; Chardev *chr; int fw_size, fit_err; bool is_64b; if ((machine->ram_size % G_BYTE) || (machine->ram_size > (2 * G_BYTE))) { error_report("Memory size must be 1GB or 2GB"); exit(1); } cpu_model = machine->cpu_model ?: "I6400"; dev = qdev_create(NULL, TYPE_MIPS_BOSTON); qdev_init_nofail(dev); s = BOSTON(dev); s->mach = machine; s->cps = g_new0(MIPSCPSState, 1); if (!cpu_supports_cps_smp(cpu_model)) { error_report("Boston requires CPUs which support CPS"); exit(1); } is_64b = cpu_supports_isa(cpu_model, ISA_MIPS64); object_initialize(s->cps, sizeof(MIPSCPSState), TYPE_MIPS_CPS); qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default()); object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err); object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err); object_property_set_bool(OBJECT(s->cps), true, "realized", &err); if (err != NULL) { error_report("%s", error_get_pretty(err)); exit(1); } sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1); flash = g_new(MemoryRegion, 1); memory_region_init_rom_device(flash, NULL, &boston_flash_ops, s, "boston.flash", 128 * M_BYTE, &err); memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); ddr = g_new(MemoryRegion, 1); memory_region_allocate_system_memory(ddr, NULL, "boston.ddr", machine->ram_size); memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0); ddr_low_alias = g_new(MemoryRegion, 1); memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", ddr, 0, MIN(machine->ram_size, (256 * M_BYTE))); memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); xilinx_pcie_init(sys_mem, 0, 0x10000000, 32 * M_BYTE, 0x40000000, 1 * G_BYTE, get_cps_irq(s->cps, 2), false); xilinx_pcie_init(sys_mem, 1, 0x12000000, 32 * M_BYTE, 0x20000000, 512 * M_BYTE, get_cps_irq(s->cps, 1), false); pcie2 = xilinx_pcie_init(sys_mem, 2, 0x14000000, 32 * M_BYTE, 0x16000000, 1 * M_BYTE, get_cps_irq(s->cps, 0), true); platreg = g_new(MemoryRegion, 1); memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, "boston-platregs", 0x1000); memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); if (!serial_hds[0]) { serial_hds[0] = qemu_chr_new("serial0", "null"); } s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, get_cps_irq(s->cps, 3), 10000000, serial_hds[0], DEVICE_NATIVE_ENDIAN); lcd = g_new(MemoryRegion, 1); memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); chr = qemu_chr_new("lcd", "vc:320x240"); qemu_chr_fe_init(&s->lcd_display, chr, NULL); qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, boston_lcd_event, s, NULL, true); ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, PCI_DEVFN(0, 0), true, TYPE_ICH9_AHCI); g_assert(ARRAY_SIZE(hd) == ICH_AHCI(ahci)->ahci.ports); ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); ahci_ide_create_devs(ahci, hd); if (machine->firmware) { fw_size = load_image_targphys(machine->firmware, 0x1fc00000, 4 * M_BYTE); if (fw_size == -1) { error_printf("unable to load firmware image '%s'\n", machine->firmware); exit(1); } } else if (machine->kernel_filename) { fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); if (fit_err) { error_printf("unable to load FIT image\n"); exit(1); } gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, s->kernel_entry, s->fdt_base, is_64b); } else if (!qtest_enabled()) { error_printf("Please provide either a -kernel or -bios argument\n"); exit(1); } }
static void fsl_imx25_realize(DeviceState *dev, Error **errp) { FslIMX25State *s = FSL_IMX25(dev); uint8_t i; Error *err = NULL; object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); if (err) { error_propagate(errp, err); return; } object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR); /* Initialize all UARTs */ for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { static const struct { hwaddr addr; unsigned int irq; } serial_table[FSL_IMX25_NUM_UARTS] = { { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ }, { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ }, { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ }, { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ }, { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ } }; if (i < MAX_SERIAL_PORTS) { CharDriverState *chr; chr = serial_hds[i]; if (!chr) { char label[20]; snprintf(label, sizeof(label), "imx31.uart%d", i); chr = qemu_chr_new(label, "null", NULL); } qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); } object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, qdev_get_gpio_in(DEVICE(&s->avic), serial_table[i].irq)); } /* Initialize all GPT timers */ for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { static const struct { hwaddr addr; unsigned int irq; } gpt_table[FSL_IMX25_NUM_GPTS] = { { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ }, { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ }, { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ }, { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ } }; s->gpt[i].ccm = DEVICE(&s->ccm); object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, qdev_get_gpio_in(DEVICE(&s->avic), gpt_table[i].irq)); } /* Initialize all EPIT timers */ for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { static const struct { hwaddr addr; unsigned int irq; } epit_table[FSL_IMX25_NUM_EPITS] = { { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ }, { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ } }; s->epit[i].ccm = DEVICE(&s->ccm); object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, qdev_get_gpio_in(DEVICE(&s->avic), epit_table[i].irq)); } qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]); object_property_set_bool(OBJECT(&s->fec), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0, qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ)); /* Initialize all I2C */ for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { static const struct { hwaddr addr; unsigned int irq; } i2c_table[FSL_IMX25_NUM_I2CS] = { { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ }, { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ }, { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ } }; object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, qdev_get_gpio_in(DEVICE(&s->avic), i2c_table[i].irq)); } /* Initialize all GPIOs */ for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { static const struct { hwaddr addr; unsigned int irq; } gpio_table[FSL_IMX25_NUM_GPIOS] = { { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ }, { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ }, { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ }, { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ } }; object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); /* Connect GPIO IRQ to PIC */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, qdev_get_gpio_in(DEVICE(&s->avic), gpio_table[i].irq)); } /* initialize 2 x 16 KB ROM */ memory_region_init_rom_device(&s->rom[0], NULL, NULL, NULL, "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR, &s->rom[0]); memory_region_init_rom_device(&s->rom[1], NULL, NULL, NULL, "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR, &s->rom[1]); /* initialize internal RAM (128 KB) */ memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE, &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR, &s->iram); vmstate_register_ram_global(&s->iram); /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */ memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias", &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE); memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR, &s->iram_alias); }
static void fsl_imx31_realize(DeviceState *dev, Error **errp) { FslIMX31State *s = FSL_IMX31(dev); uint16_t i; Error *err = NULL; object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); if (err) { error_propagate(errp, err); return; } object_property_set_bool(OBJECT(&s->avic), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0, qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1, qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ)); object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR); /* Initialize all UARTS */ for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) { static const struct { hwaddr addr; unsigned int irq; } serial_table[FSL_IMX31_NUM_UARTS] = { { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ }, { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ }, }; if (i < MAX_SERIAL_PORTS) { CharDriverState *chr; chr = serial_hds[i]; if (!chr) { char label[20]; snprintf(label, sizeof(label), "imx31.uart%d", i); chr = qemu_chr_new(label, "null", NULL); } qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); } object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, qdev_get_gpio_in(DEVICE(&s->avic), serial_table[i].irq)); } s->gpt.ccm = DEVICE(&s->ccm); object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ)); /* Initialize all EPIT timers */ for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) { static const struct { hwaddr addr; unsigned int irq; } epit_table[FSL_IMX31_NUM_EPITS] = { { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ }, { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ }, }; s->epit[i].ccm = DEVICE(&s->ccm); object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, qdev_get_gpio_in(DEVICE(&s->avic), epit_table[i].irq)); } /* Initialize all I2C */ for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) { static const struct { hwaddr addr; unsigned int irq; } i2c_table[FSL_IMX31_NUM_I2CS] = { { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ }, { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ }, { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ } }; /* Initialize the I2C */ object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } /* Map I2C memory */ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); /* Connect I2C IRQ to PIC */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, qdev_get_gpio_in(DEVICE(&s->avic), i2c_table[i].irq)); } /* Initialize all GPIOs */ for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) { static const struct { hwaddr addr; unsigned int irq; } gpio_table[FSL_IMX31_NUM_GPIOS] = { { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ }, { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ }, { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ } }; object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel", &error_abort); object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err); if (err) { error_propagate(errp, err); return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); /* Connect GPIO IRQ to PIC */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, qdev_get_gpio_in(DEVICE(&s->avic), gpio_table[i].irq)); } /* On a real system, the first 16k is a `secure boot rom' */ memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL, "imx31.secure_rom", FSL_IMX31_SECURE_ROM_SIZE, &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR, &s->secure_rom); /* There is also a 16k ROM */ memory_region_init_rom_device(&s->rom, NULL, NULL, NULL, "imx31.rom", FSL_IMX31_ROM_SIZE, &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR, &s->rom); /* initialize internal RAM (16 KB) */ memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE, &err); if (err) { error_propagate(errp, err); return; } memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR, &s->iram); vmstate_register_ram_global(&s->iram); /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */ memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias", &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE); memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR, &s->iram_alias); }