/*
* Determine device configuration for a machine.
*/
void
cpu_configure(void)
{
intr_init();
calc_delayconst();
/* Make sure that timers run at CPU frequency */
mtdcr(DCR_CPC0_CR1, mfdcr(DCR_CPC0_CR1) & ~CPC0_CR1_CETE);
if (config_rootfound("plb", &local_plb_devs) == NULL)
panic("configure: plb not configured");
printf("biomask %x netmask %x ttymask %x\n", (u_short)imask[IPL_BIO],
(u_short)imask[IPL_NET], (u_short)imask[IPL_TTY]);
(void)spl0();
/*
* Now allow hardware interrupts.
*/
asm volatile ("wrteei 1");
}
/*************************************************************************
* void l2cache_enable()
*
************************************************************************/
static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
{
mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */
mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */
mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */
mtdcr( L2_CACHE_SNP1, 0 );
__asm__ volatile ("sync"); /* msync */
mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */
__asm__ volatile ("sync");
}
int wait_for_dram_init_complete(void)
{
u32 val;
int wait = 0;
/*
* Wait for 'DRAM initialization complete' bit in status register
*/
mtdcr(ddrcfga, DDR0_00);
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
/* 'DRAM initialization complete' bit */
return 0;
else
wait++;
}
debug("DRAM initialization complete bit in status register did not rise\n");
return -1;
}
static int emulate_mfdcr(struct kvm_vcpu *vcpu, int rt, int dcrn)
{
/* The guest may access CPR0 registers to determine the timebase
* frequency, and it must know the real host frequency because it
* can directly access the timebase registers.
*
* It would be possible to emulate those accesses in userspace,
* but userspace can really only figure out the end frequency.
* We could decompose that into the factors that compute it, but
* that's tricky math, and it's easier to just report the real
* CPR0 values.
*/
switch (dcrn) {
case DCRN_CPR0_CONFIG_ADDR:
kvmppc_set_gpr(vcpu, rt, vcpu->arch.cpr0_cfgaddr);
break;
case DCRN_CPR0_CONFIG_DATA:
local_irq_disable();
mtdcr(DCRN_CPR0_CONFIG_ADDR,
vcpu->arch.cpr0_cfgaddr);
kvmppc_set_gpr(vcpu, rt,
mfdcr(DCRN_CPR0_CONFIG_DATA));
local_irq_enable();
break;
default:
vcpu->run->dcr.dcrn = dcrn;
vcpu->run->dcr.data = 0;
vcpu->run->dcr.is_write = 0;
vcpu->arch.dcr_is_write = 0;
vcpu->arch.io_gpr = rt;
vcpu->arch.dcr_needed = 1;
kvmppc_account_exit(vcpu, DCR_EXITS);
return EMULATE_DO_DCR;
}
return EMULATE_DONE;
}
void __ft_board_setup(void *blob, bd_t *bd)
{
int rc;
int i;
u32 bxcr;
u32 ranges[EBC_NUM_BANKS * 4];
u32 *p = ranges;
char *ebc_path = "/plb/opb/ebc";
ft_cpu_setup(blob, bd);
/*
* Read 4xx EBC bus bridge registers to get mappings of the
* peripheral banks into the OPB/PLB address space
*/
for (i = 0; i < EBC_NUM_BANKS; i++) {
mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
bxcr = mfdcr(EBC0_CFGDATA);
if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
*p++ = i;
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS_MASK;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
}
}
/* Some 405 PPC's have EBC as direct PLB child in the dts */
if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
strcpy(ebc_path, "/plb/ebc");
rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
(p - ranges) * sizeof(u32), 1);
if (rc) {
printf("Unable to update property EBC mappings, err=%s\n",
fdt_strerror(rc));
}
}
/*-----------------------------------------------------------------------------+
* wait_for_dlllock.
+----------------------------------------------------------------------------*/
static int wait_for_dlllock(void)
{
unsigned long val;
int wait = 0;
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_17);
val = DDR0_17_DLLLOCKREG_UNLOCKED;
while (wait != 0xffff) {
val = mfdcr(ddrcfgd);
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
/* dlllockreg bit on */
return 0;
else
wait++;
}
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
debug("Waiting for dlllockreg bit to raise\n");
return -1;
}
int board_early_init_f (void)
{
uint reg;
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr( ebccfga, xbcfg );
reg = mfdcr( ebccfgd );
mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */
mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */
mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */
/* test-only: other regs still missing... */
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr( uic0sr, 0xffffffff ); /* clear all */
mtdcr( uic0er, 0x00000000 ); /* disable all */
mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */
mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */
mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */
mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */
mtdcr( uic0sr, 0xffffffff ); /* clear all */
mtdcr( uic1sr, 0xffffffff ); /* clear all */
mtdcr( uic1er, 0x00000000 ); /* disable all */
mtdcr( uic1cr, 0x00000000 ); /* all non-critical */
mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */
mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */
mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */
mtdcr( uic1sr, 0xffffffff ); /* clear all */
return 0;
}
int checkcpu (void)
{
#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
uint pvr = get_pvr();
ulong clock = gd->cpu_clk;
char buf[32];
#if !defined(CONFIG_IOP480)
char addstr[64] = "";
sys_info_t sys_info;
puts ("CPU: ");
get_sys_info(&sys_info);
puts("AMCC PowerPC 4");
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX)
puts("05");
#endif
#if defined(CONFIG_440)
puts("40");
#endif
switch (pvr) {
case PVR_405GP_RB:
puts("GP Rev. B");
break;
case PVR_405GP_RC:
puts("GP Rev. C");
break;
case PVR_405GP_RD:
puts("GP Rev. D");
break;
#ifdef CONFIG_405GP
case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
puts("GP Rev. E");
break;
#endif
case PVR_405CR_RA:
puts("CR Rev. A");
break;
case PVR_405CR_RB:
puts("CR Rev. B");
break;
#ifdef CONFIG_405CR
case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
puts("CR Rev. C");
break;
#endif
case PVR_405GPR_RB:
puts("GPr Rev. B");
break;
case PVR_405EP_RB:
puts("EP Rev. B");
break;
case PVR_405EZ_RA:
puts("EZ Rev. A");
break;
case PVR_405EX1_RA:
puts("EX Rev. A");
strcpy(addstr, "Security support");
break;
case PVR_405EX2_RA:
puts("EX Rev. A");
strcpy(addstr, "No Security support");
break;
case PVR_405EXR1_RA:
puts("EXr Rev. A");
strcpy(addstr, "Security support");
break;
case PVR_405EXR2_RA:
puts("EXr Rev. A");
strcpy(addstr, "No Security support");
break;
#if defined(CONFIG_440)
case PVR_440GP_RB:
puts("GP Rev. B");
/* See errata 1.12: CHIP_4 */
if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
(mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
puts ( "\n\t CPC0_SYSx DCRs corrupted. "
"Resetting chip ...\n");
udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
do_chip_reset ( mfdcr(cpc0_strp0),
mfdcr(cpc0_strp1) );
}
break;
case PVR_440GP_RC:
puts("GP Rev. C");
break;
case PVR_440GX_RA:
puts("GX Rev. A");
break;
case PVR_440GX_RB:
puts("GX Rev. B");
break;
case PVR_440GX_RC:
puts("GX Rev. C");
break;
case PVR_440GX_RF:
puts("GX Rev. F");
break;
case PVR_440EP_RA:
puts("EP Rev. A");
break;
#ifdef CONFIG_440EP
case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
puts("EP Rev. B");
break;
case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
puts("EP Rev. C");
break;
#endif /* CONFIG_440EP */
#ifdef CONFIG_440GR
case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
puts("GR Rev. A");
break;
case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
puts("GR Rev. B");
break;
#endif /* CONFIG_440GR */
#endif /* CONFIG_440 */
#ifdef CONFIG_440EPX
case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
puts("EPx Rev. A");
strcpy(addstr, "Security/Kasumi support");
break;
case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
puts("EPx Rev. A");
strcpy(addstr, "No Security/Kasumi support");
break;
#endif /* CONFIG_440EPX */
#ifdef CONFIG_440GRX
case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
puts("GRx Rev. A");
strcpy(addstr, "Security/Kasumi support");
break;
case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
puts("GRx Rev. A");
strcpy(addstr, "No Security/Kasumi support");
break;
#endif /* CONFIG_440GRX */
case PVR_440SP_6_RAB:
puts("SP Rev. A/B");
strcpy(addstr, "RAID 6 support");
break;
case PVR_440SP_RAB:
puts("SP Rev. A/B");
strcpy(addstr, "No RAID 6 support");
break;
case PVR_440SP_6_RC:
puts("SP Rev. C");
strcpy(addstr, "RAID 6 support");
break;
case PVR_440SP_RC:
puts("SP Rev. C");
strcpy(addstr, "No RAID 6 support");
break;
case PVR_440SPe_6_RA:
puts("SPe Rev. A");
strcpy(addstr, "RAID 6 support");
break;
case PVR_440SPe_RA:
puts("SPe Rev. A");
strcpy(addstr, "No RAID 6 support");
break;
case PVR_440SPe_6_RB:
puts("SPe Rev. B");
strcpy(addstr, "RAID 6 support");
break;
case PVR_440SPe_RB:
puts("SPe Rev. B");
strcpy(addstr, "No RAID 6 support");
break;
default:
printf (" UNKNOWN (PVR=%08x)", pvr);
break;
}
printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
sys_info.freqPLB / 1000000,
get_OPB_freq() / 1000000,
sys_info.freqEBC / 1000000);
if (addstr[0] != 0)
printf(" %s\n", addstr);
#if defined(I2C_BOOTROM)
printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
#endif /* I2C_BOOTROM */
#if defined(SDR0_PINSTP_SHIFT)
printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
#endif /* SDR0_PINSTP_SHIFT */
#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
#endif
#if defined(PCI_ASYNC)
if (pci_async_enabled()) {
printf (", PCI async ext clock used");
} else {
printf (", PCI sync clock at %lu MHz",
sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
}
#endif
#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
putc('\n');
#endif
#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
printf (" 16 kB I-Cache 16 kB D-Cache");
#elif defined(CONFIG_440)
printf (" 32 kB I-Cache 32 kB D-Cache");
#else
printf (" 16 kB I-Cache %d kB D-Cache",
((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
#endif /* !defined(CONFIG_IOP480) */
#if defined(CONFIG_IOP480)
printf ("PLX IOP480 (PVR=%08x)", pvr);
printf (" at %s MHz:", strmhz(buf, clock));
printf (" %u kB I-Cache", 4);
printf (" %u kB D-Cache", 2);
#endif
#endif /* !defined(CONFIG_405) */
putc ('\n');
return 0;
}
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
base_b0 = FLASH_BASE0_PRELIM;
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 << 20);
}
base_b1 = FLASH_BASE1_PRELIM;
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1) {
if (size_b1 < (1 << 20)) {
/* minimum CS size on PPC405GP is 1MB !!! */
size_b1 = 1 << 20;
}
base_b1 = -size_b1;
mtdcr (EBC0_CFGADDR, PB0CR);
pbcr = mfdcr (EBC0_CFGDATA);
mtdcr (EBC0_CFGADDR, PB0CR);
pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
mtdcr (EBC0_CFGDATA, pbcr);
#if 0 /* test-only */
printf("size_b1=%x base_b1=%x PB1CR = %x\n",
size_b1, base_b1, pbcr); /* test-only */
#endif
}
if (size_b0) {
if (size_b0 < (1 << 20)) {
/* minimum CS size on PPC405GP is 1MB !!! */
size_b0 = 1 << 20;
}
base_b0 = base_b1 - size_b0;
mtdcr (EBC0_CFGADDR, PB1CR);
pbcr = mfdcr (EBC0_CFGDATA);
mtdcr (EBC0_CFGADDR, PB1CR);
pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
mtdcr (EBC0_CFGDATA, pbcr);
#if 0 /* test-only */
printf("size_b0=%x base_b0=%x PB0CR = %x\n",
size_b0, base_b0, pbcr); /* test-only */
#endif
}
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
flash_get_offsets (base_b0, &flash_info[0]);
/* monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
base_b0 + size_b0 - monitor_flash_len,
base_b0 + size_b0 - 1, &flash_info[0]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
flash_get_offsets (base_b1, &flash_info[1]);
/* monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
base_b1 + size_b1 - monitor_flash_len,
base_b1 + size_b1 - 1, &flash_info[1]);
/* monitor protection OFF by default (one is enough) */
flash_protect (FLAG_PROTECT_CLEAR,
base_b0 + size_b0 - monitor_flash_len,
base_b0 + size_b0 - 1, &flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
return (size_b0 + size_b1);
}
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
base_b0 = FLASH_BASE0_PRELIM;
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 << 20);
}
base_b1 = FLASH_BASE1_PRELIM;
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr (ebccfga, pb0cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb0cr);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr (ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
}
if (size_b0) {
mtdcr (ebccfga, pb1cr);
pbcr = mfdcr (ebccfgd);
mtdcr (ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr (ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
}
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
flash_get_offsets (base_b0, &flash_info[0]);
/* monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
base_b0 + size_b0 - monitor_flash_len,
base_b0 + size_b0 - 1, &flash_info[0]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
flash_get_offsets (base_b1, &flash_info[1]);
/* monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
base_b1 + size_b1 - monitor_flash_len,
base_b1 + size_b1 - 1, &flash_info[1]);
/* monitor protection OFF by default (one is enough) */
flash_protect (FLAG_PROTECT_CLEAR,
base_b0 + size_b0 - monitor_flash_len,
base_b0 + size_b0 - 1, &flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
return (size_b0 + size_b1);
}
void
ppc4xx_enable_dma(unsigned int dmanr)
{
unsigned int control;
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
unsigned int status_bits[] = { DMA_CS0 | DMA_TS0 | DMA_CH0_ERR,
DMA_CS1 | DMA_TS1 | DMA_CH1_ERR,
DMA_CS2 | DMA_TS2 | DMA_CH2_ERR,
DMA_CS3 | DMA_TS3 | DMA_CH3_ERR};
if (p_dma_ch->in_use) {
printk("enable_dma: channel %d in use\n", dmanr);
return;
}
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("enable_dma: bad channel: %d\n", dmanr);
return;
}
if (p_dma_ch->mode == DMA_MODE_READ) {
/* peripheral to memory */
ppc4xx_set_src_addr(dmanr, 0);
ppc4xx_set_dst_addr(dmanr, p_dma_ch->addr);
} else if (p_dma_ch->mode == DMA_MODE_WRITE) {
/* memory to peripheral */
ppc4xx_set_src_addr(dmanr, p_dma_ch->addr);
ppc4xx_set_dst_addr(dmanr, 0);
}
/* for other xfer modes, the addresses are already set */
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
control &= ~(DMA_TM_MASK | DMA_TD); /* clear all mode bits */
if (p_dma_ch->mode == DMA_MODE_MM) {
/* software initiated memory to memory */
control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
}
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
/*
* Clear the CS, TS, RI bits for the channel from DMASR. This
* has been observed to happen correctly only after the mode and
* ETD/DCE bits in DMACRx are set above. Must do this before
* enabling the channel.
*/
mtdcr(DCRN_DMASR, status_bits[dmanr]);
/*
* For device-paced transfers, Terminal Count Enable apparently
* must be on, and this must be turned on after the mode, etc.
* bits are cleared above (at least on Redwood-6).
*/
if ((p_dma_ch->mode == DMA_MODE_MM_DEVATDST) ||
(p_dma_ch->mode == DMA_MODE_MM_DEVATSRC))
control |= DMA_TCE_ENABLE;
/*
* Now enable the channel.
*/
control |= (p_dma_ch->mode | DMA_CE_ENABLE);
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
p_dma_ch->in_use = 1;
}
struct bi_record *
decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
{
#ifdef INTERACTIVE_CONSOLE
int timer = 0;
char ch;
#endif
char *cp;
struct bi_record *rec;
unsigned long initrd_loc = 0, TotalMemory = 0;
#if defined(CONFIG_SERIAL_8250_CONSOLE) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
com_port = serial_init(0, NULL);
#endif
#if defined(PPC4xx_EMAC0_MR0)
/* Reset MAL */
mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR);
/* Wait for reset */
while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {};
/* Reset EMAC */
*(volatile unsigned long *)PPC4xx_EMAC0_MR0 = 0x20000000;
__asm__ __volatile__("eieio");
#endif
/*
* Call get_mem_size(), which is memory controller dependent,
* and we must have the correct file linked in here.
*/
TotalMemory = get_mem_size();
/* assume the chunk below 8M is free */
end_avail = (char *)0x00800000;
/*
* Reveal where we were loaded at and where we
* were relocated to.
*/
puts("loaded at: "); puthex(load_addr);
puts(" "); puthex((unsigned long)(load_addr + (4*num_words)));
puts("\n");
if ( (unsigned long)load_addr != (unsigned long)&start )
{
puts("relocated to: "); puthex((unsigned long)&start);
puts(" ");
puthex((unsigned long)((unsigned long)&start + (4*num_words)));
puts("\n");
}
/*
* We link ourself to 0x00800000. When we run, we relocate
* ourselves there. So we just need __image_begin for the
* start. -- Tom
*/
zimage_start = (char *)(unsigned long)(&__image_begin);
zimage_size = (unsigned long)(&__image_end) -
(unsigned long)(&__image_begin);
initrd_size = (unsigned long)(&__ramdisk_end) -
(unsigned long)(&__ramdisk_begin);
/*
* The zImage and initrd will be between start and _end, so they've
* already been moved once. We're good to go now. -- Tom
*/
avail_ram = (char *)PAGE_ALIGN((unsigned long)_end);
puts("zimage at: "); puthex((unsigned long)zimage_start);
puts(" "); puthex((unsigned long)(zimage_size+zimage_start));
puts("\n");
if ( initrd_size ) {
puts("initrd at: ");
puthex((unsigned long)(&__ramdisk_begin));
puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n");
}
#ifndef CONFIG_40x /* don't overwrite the 40x image located at 0x00400000! */
avail_ram = (char *)0x00400000;
#endif
end_avail = (char *)0x00800000;
puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" ");
puthex((unsigned long)end_avail); puts("\n");
if (keyb_present)
CRT_tstc(); /* Forces keyboard to be initialized */
/* Display standard Linux/PPC boot prompt for kernel args */
puts("\nLinux/PPC load: ");
cp = cmd_line;
memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
while ( *cp ) putc(*cp++);
#ifdef INTERACTIVE_CONSOLE
/*
* If they have a console, allow them to edit the command line.
* Otherwise, don't bother wasting the five seconds.
*/
while (timer++ < 5*1000) {
if (tstc()) {
while ((ch = getc()) != '\n' && ch != '\r') {
/* Test for backspace/delete */
if (ch == '\b' || ch == '\177') {
if (cp != cmd_line) {
cp--;
puts("\b \b");
}
/* Test for ^x/^u (and wipe the line) */
} else if (ch == '\030' || ch == '\025') {
while (cp != cmd_line) {
cp--;
puts("\b \b");
}
} else {
*cp++ = ch;
putc(ch);
}
}
break; /* Exit 'timer' loop */
}
udelay(1000); /* 1 msec */
}
*cp = 0;
#endif
puts("\n");
puts("Uncompressing Linux...");
gunzip(NULL, 0x400000, zimage_start, &zimage_size);
puts("done.\n");
/* get the bi_rec address */
rec = bootinfo_addr(zimage_size);
/* We need to make sure that the initrd and bi_recs do not
* overlap. */
if ( initrd_size ) {
unsigned long rec_loc = (unsigned long) rec;
initrd_loc = (unsigned long)(&__ramdisk_begin);
/* If the bi_recs are in the middle of the current
* initrd, move the initrd to the next MB
* boundary. */
if ((rec_loc > initrd_loc) &&
((initrd_loc + initrd_size) > rec_loc)) {
initrd_loc = _ALIGN((unsigned long)(zimage_size)
+ (2 << 20) - 1, (2 << 20));
memmove((void *)initrd_loc, &__ramdisk_begin,
initrd_size);
puts("initrd moved: "); puthex(initrd_loc);
puts(" "); puthex(initrd_loc + initrd_size);
puts("\n");
}
}
bootinfo_init(rec);
if ( TotalMemory )
bootinfo_append(BI_MEMSIZE, sizeof(int), (void*)&TotalMemory);
bootinfo_append(BI_CMD_LINE, strlen(cmd_line)+1, (void*)cmd_line);
/* add a bi_rec for the initrd if it exists */
if (initrd_size) {
unsigned long initrd[2];
initrd[0] = initrd_loc;
initrd[1] = initrd_size;
bootinfo_append(BI_INITRD, sizeof(initrd), &initrd);
}
puts("Now booting the kernel\n");
serial_close(com_port);
return rec;
}
/*
* Create a scatter/gather list handle. This is simply a structure which
* describes a scatter/gather list.
*
* A handle is returned in "handle" which the driver should save in order to
* be able to access this list later. A chunk of memory will be allocated
* to be used by the API for internal management purposes, including managing
* the sg list and allocating memory for the sgl descriptors. One page should
* be more than enough for that purpose. Perhaps it's a bit wasteful to use
* a whole page for a single sg list, but most likely there will be only one
* sg list per channel.
*
* Interrupt notes:
* Each sgl descriptor has a copy of the DMA control word which the DMA engine
* loads in the control register. The control word has a "global" interrupt
* enable bit for that channel. Interrupts are further qualified by a few bits
* in the sgl descriptor count register. In order to setup an sgl, we have to
* know ahead of time whether or not interrupts will be enabled at the completion
* of the transfers. Thus, enable_dma_interrupt()/disable_dma_interrupt() MUST
* be called before calling alloc_dma_handle(). If the interrupt mode will never
* change after powerup, then enable_dma_interrupt()/disable_dma_interrupt()
* do not have to be called -- interrupts will be enabled or disabled based
* on how the channel was configured after powerup by the hw_init_dma_channel()
* function. Each sgl descriptor will be setup to interrupt if an error occurs;
* however, only the last descriptor will be setup to interrupt. Thus, an
* interrupt will occur (if interrupts are enabled) only after the complete
* sgl transfer is done.
*/
int
ppc4xx_alloc_dma_handle(sgl_handle_t * phandle, unsigned int mode, unsigned int dmanr)
{
sgl_list_info_t *psgl;
dma_addr_t dma_addr;
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
uint32_t sg_command;
void *ret;
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_alloc_dma_handle: invalid channel 0x%x\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
if (!phandle) {
printk("ppc4xx_alloc_dma_handle: null handle pointer\n");
return DMA_STATUS_NULL_POINTER;
}
/* Get a page of memory, which is zeroed out by consistent_alloc() */
ret = consistent_alloc(GFP_KERNEL, DMA_PPC4xx_SIZE, &dma_addr);
if (ret != NULL) {
memset(ret, 0, DMA_PPC4xx_SIZE);
psgl = (sgl_list_info_t *) ret;
}
if (psgl == NULL) {
*phandle = (sgl_handle_t) NULL;
return DMA_STATUS_OUT_OF_MEMORY;
}
psgl->dma_addr = dma_addr;
psgl->dmanr = dmanr;
/*
* Modify and save the control word. These words will be
* written to each sgl descriptor. The DMA engine then
* loads this control word into the control register
* every time it reads a new descriptor.
*/
psgl->control = p_dma_ch->control;
/* Clear all mode bits */
psgl->control &= ~(DMA_TM_MASK | DMA_TD);
/* Save control word and mode */
psgl->control |= (mode | DMA_CE_ENABLE);
/* In MM mode, we must set ETD/TCE */
if (mode == DMA_MODE_MM)
psgl->control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
if (p_dma_ch->int_enable) {
/* Enable channel interrupt */
psgl->control |= DMA_CIE_ENABLE;
} else {
psgl->control &= ~DMA_CIE_ENABLE;
}
sg_command = mfdcr(DCRN_ASGC);
switch (dmanr) {
case 0:
sg_command |= SSG0_MASK_ENABLE;
break;
case 1:
sg_command |= SSG1_MASK_ENABLE;
break;
case 2:
sg_command |= SSG2_MASK_ENABLE;
break;
case 3:
sg_command |= SSG3_MASK_ENABLE;
break;
default:
printk("ppc4xx_alloc_dma_handle: bad channel: %d\n", dmanr);
ppc4xx_free_dma_handle((sgl_handle_t) psgl);
*phandle = (sgl_handle_t) NULL;
return DMA_STATUS_BAD_CHANNEL;
}
/* Enable SGL control access */
mtdcr(DCRN_ASGC, sg_command);
psgl->sgl_control = SG_ERI_ENABLE | SG_LINK;
if (p_dma_ch->int_enable) {
if (p_dma_ch->tce_enable)
psgl->sgl_control |= SG_TCI_ENABLE;
else
psgl->sgl_control |= SG_ETI_ENABLE;
}
*phandle = (sgl_handle_t) psgl;
return DMA_STATUS_GOOD;
}
static int ppc4xx_pic_get_irq(struct pt_regs *regs)
{
u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
return uic0 ? 32 - ffs(uic0) : -1;
}
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
bd_t *bd = gd->bd;
char * tmp; /* Temporary char pointer */
unsigned long cntrl0Reg;
#ifdef CONFIG_CPCI405_VER2
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
int index;
int i;
/*
* On CPCI-405 version 2 the environment is saved in eeprom!
* FPGA can be gzip compressed (malloc) and booted this late.
*/
if (cpci405_version() >= 2) {
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00300000);
dst = malloc(CFG_FPGA_MAX_SIZE);
if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
if (status != 0) {
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("FPGA: %s\n", &(dst[index+1]));
index += len+3;
}
putc ('\n');
/* delayed reboot */
for (i=20; i>0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index=0;index<1000;index++)
udelay(1000);
}
putc ('\n');
do_reset(NULL, 0, 0, NULL);
}
/* restore gpio/cs settings */
mtdcr(cntrl0, cntrl0Reg);
puts("FPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
len = dst[index];
printf("%s ", &(dst[index+1]));
index += len+3;
}
putc ('\n');
free(dst);
/*
* Reset FPGA via FPGA_DATA pin
*/
SET_FPGA(FPGA_PRG | FPGA_CLK);
udelay(1000); /* wait 1ms */
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
if (cpci405_version() == 3) {
volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
/*
* Enable outputs in fpga on version 3 board
*/
*fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
/*
* Set outputs to 0
*/
*leds = 0x00;
/*
* Reset external DUART
*/
*fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
udelay(100);
*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
}
}
else {
puts("\n*** U-Boot Version does not match Board Version!\n");
puts("*** CPCI-405 Version 1.x detected!\n");
puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
}
#else /* CONFIG_CPCI405_VER2 */
/*
* Generate last byte of ip-addr from code-plug @ 0xf0000400
*/
if (ctermm2()) {
char str[32];
unsigned char ipbyte = *(unsigned char *)0xf0000400;
/*
* Only overwrite ip-addr with allowed values
*/
if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
sprintf(str, "%ld.%ld.%ld.%ld",
(bd->bi_ip_addr & 0xff000000) >> 24,
(bd->bi_ip_addr & 0x00ff0000) >> 16,
(bd->bi_ip_addr & 0x0000ff00) >> 8,
(bd->bi_ip_addr & 0x000000ff));
setenv("ipaddr", str);
}
}
int misc_init_r(void)
{
u32 pbcr;
int size_val = 0;
u32 reg;
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1, sdr0_srst;
/*
* FLASH stuff...
*/
/* Re-do sizing to get full correct info */
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
mfebc(PB0CR, pbcr);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtebc(PB0CR, pbcr);
/*
* Re-check to get correct base address
*/
flash_get_size(gd->bd->bi_flashstart, 0);
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
&flash_info[cfi_flash_num_flash_banks - 1]);
/* Env protection ON by default */
flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
&flash_info[cfi_flash_num_flash_banks - 1]);
/*
* USB suff...
*/
/* Reset USB */
/* Reset of USB2PHY0 must be active at least 10 us */
mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
udelay(2000);
mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
udelay(2000);
/* Errata CHIP_6 */
/* 1. Set internal PHY configuration */
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
/*
* An 8-bit/60MHz interface is the only possible alternative
* when connecting the Device to the PHY
*/
usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
/* 2. De-assert internal PHY reset */
mfsdr(SDR0_SRST1, sdr0_srst);
sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
mtsdr(SDR0_SRST1, sdr0_srst);
/* 3. Wait for more than 1 ms */
udelay(2000);
/* 4. De-assert USB 2.0 Host main reset */
mfsdr(SDR0_SRST0, sdr0_srst);
sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
mtsdr(SDR0_SRST0, sdr0_srst);
udelay(1000);
/* 5. De-assert reset of OPB2 cores */
mfsdr(SDR0_SRST1, sdr0_srst);
sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
mtsdr(SDR0_SRST1, sdr0_srst);
udelay(1000);
/* 6. Set EHCI Configure FLAG */
/* 7. Reassert internal PHY reset: */
mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
udelay(1000);
/*
* Clear resets
*/
mtsdr(SDR0_SRST1, 0x00000000);
mtsdr(SDR0_SRST0, 0x00000000);
printf("USB: Host(int phy) Device(ext phy)\n");
/*
* Clear PLB4A0_ACR[WRP]
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
mtdcr(PLB4A0_ACR, reg);
/*
* Init matrix keyboard
*/
misc_init_r_kbd();
return 0;
}
/*-----------------------------------------------------------------------------+
* denali_core_search_data_eye.
+----------------------------------------------------------------------------*/
void denali_core_search_data_eye(unsigned long memory_size)
{
int k, j;
u32 val;
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
volatile u32 *ram_pointer;
u32 test[NUM_TRIES] = {
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'wr_dqs_shift'
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
* ----------------------------------------------------------*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
passing_cases = 0;
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
* ----------------------------------------------------------*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
printf("denali_core_search_data_eye!!!\n");
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
wr_dqs_shift, dll_dqs_delay_X);
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
/* write values */
for (j=0; j<NUM_TRIES; j++) {
ram_pointer[j] = test[j];
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
}
/* read values back */
for (j=0; j<NUM_TRIES; j++) {
for (k=0; k<NUM_READS; k++) {
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
if (ram_pointer[j] != test[j])
break;
}
/* read error */
if (k != NUM_READS)
break;
}
/* See if the dll_dqs_delay_X value passed.*/
if (j < NUM_TRIES) {
/* Failed */
passing_cases = 0;
/* break; */
} else {
/* Passed */
if (passing_cases == 0)
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
passing_cases++;
if (passing_cases >= max_passing_cases) {
max_passing_cases = passing_cases;
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
}
}
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
/* -----------------------------------------------------------+
* Largest passing window is now detected.
* ----------------------------------------------------------*/
/* Compute dll_dqs_delay_X value */
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
debug("DQS calibration - Window detected:\n");
debug("max_passing_cases = %d\n", max_passing_cases);
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
debug("dll_dqs_delay_X window = %d - %d\n",
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
/* -----------------------------------------------------------+
* De-assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
mtdcr(ddrcfgd, val);
/* -----------------------------------------------------------+
* Set 'wr_dqs_shift'
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_09);
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_09=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Set 'dqs_out_shift' = wr_dqs_shift + 32
* ----------------------------------------------------------*/
dqs_out_shift = wr_dqs_shift + 32;
mtdcr(ddrcfga, DDR0_22);
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
mtdcr(ddrcfgd, val);
debug("DDR0_22=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Set 'dll_dqs_delay_X'.
* ----------------------------------------------------------*/
/* dll_dqs_delay_0 */
mtdcr(ddrcfga, DDR0_17);
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_17=0x%08lx\n", val);
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
mtdcr(ddrcfga, DDR0_18);
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_18=0x%08lx\n", val);
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
mtdcr(ddrcfga, DDR0_19);
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
mtdcr(ddrcfgd, val);
debug("DDR0_19=0x%08lx\n", val);
/* -----------------------------------------------------------+
* Assert 'start' parameter.
* ----------------------------------------------------------*/
mtdcr(ddrcfga, DDR0_02);
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
mtdcr(ddrcfgd, val);
ppcMsync();
ppcMbar();
/* -----------------------------------------------------------+
* Wait for the DCC master delay line to finish calibration
* ----------------------------------------------------------*/
if (wait_for_dlllock() != 0) {
printf("dlllock did not occur !!!\n");
hang();
}
ppcMsync();
ppcMbar();
if (wait_for_dram_init_complete() != 0) {
printf("dram init complete did not occur !!!\n");
hang();
}
udelay(100); /* wait 100us to ensure init is really completed !!! */
}
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1) {
/* Setup offsets */
flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]);
/* Monitor protection ON by default */
#if 0 /* sand: */
(void)flash_protect(FLAG_PROTECT_SET,
FLASH_BASE1_PRELIM-CFG_MONITOR_LEN+size_b0,
FLASH_BASE1_PRELIM-1+size_b0,
&flash_info[0]);
#else
(void)flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
#endif
size_b1 = 0 ;
flash_info[0].size = size_b0;
} else { /* 2 banks */
size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
}
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
mtdcr(ebccfgd, pbcr);
}
size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
flash_get_offsets (base_b0, &flash_info[0]);
/* monitor protection ON by default */
#if 0 /* sand: */
(void)flash_protect(FLAG_PROTECT_SET,
FLASH_BASE1_PRELIM-CFG_MONITOR_LEN+size_b0,
FLASH_BASE1_PRELIM-1+size_b0,
&flash_info[0]);
#else
(void)flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
&flash_info[0]);
#endif
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
flash_get_offsets (base_b1, &flash_info[1]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b1+size_b1-CFG_MONITOR_LEN,
base_b1+size_b1-1,
&flash_info[1]);
/* monitor protection OFF by default (one is enough) */
(void)flash_protect(FLAG_PROTECT_CLEAR,
base_b0+size_b0-CFG_MONITOR_LEN,
base_b0+size_b0-1,
&flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
}/* else 2 banks */
return (size_b0 + size_b1);
}
int misc_init_r(void)
{
u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
int index;
int i;
unsigned long CPC0_CR0Reg;
char *str;
uchar *logo_addr;
ulong logo_size;
ushort minb, maxb;
int result;
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
CPC0_CR0Reg = mfdcr(CPC0_CR0);
mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf("GUNZIP ERROR - must RESET board to recover\n");
do_reset(NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
if (status != 0) {
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: "
"INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: "
"INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: "
"DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = dst[index];
printf("FPGA: %s\n", &(dst[index+1]));
index += len + 3;
}
putc('\n');
/* delayed reboot */
for (i = 20; i > 0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index = 0; index < 1000; index++)
udelay(1000);
}
putc('\n');
do_reset(NULL, 0, 0, NULL);
}
/* restore gpio/cs settings */
mtdcr(CPC0_CR0, CPC0_CR0Reg);
puts("FPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = dst[index];
printf("%s ", &(dst[index + 1]));
index += len + 3;
}
putc('\n');
free(dst);
/*
* Reset FPGA via FPGA_DATA pin
*/
SET_FPGA(FPGA_PRG | FPGA_CLK);
udelay(1000); /* wait 1ms */
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
/*
* Write board revision in FPGA
*/
out_be16(fpga_ctrl2,
(in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
/*
* Enable power on PS/2 interface (with reset)
*/
out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
for (i=0;i<100;i++)
udelay(1000);
udelay(1000);
out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
/*
* Enable interrupts in exar duart mcr[3]
*/
out_8(duart0_mcr, 0x08);
out_8(duart1_mcr, 0x08);
/*
* Init lcd interface and display logo
*/
str = getenv("splashimage");
if (str) {
logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
} else {
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
}
if (gd->board_type >= 6) {
result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13505_640_480_16bpp,
sizeof(regs_13505_640_480_16bpp) /
sizeof(regs_13505_640_480_16bpp[0]),
logo_addr, logo_size);
if (result && str) {
/* retry with internal image */
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13505_640_480_16bpp,
sizeof(regs_13505_640_480_16bpp) /
sizeof(regs_13505_640_480_16bpp[0]),
logo_addr, logo_size);
}
} else {
result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp) /
sizeof(regs_13806_640_480_16bpp[0]),
logo_addr, logo_size);
if (result && str) {
/* retry with internal image */
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
(uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp) /
sizeof(regs_13806_640_480_16bpp[0]),
logo_addr, logo_size);
}
}
/*
* Reset microcontroller and setup backlight PWM controller
*/
out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
for (i=0;i<10;i++)
udelay(1000);
out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
minb = 0;
maxb = 0xff;
str = getenv("lcdbl");
if (str) {
minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
if (str && (*str=',')) {
str++;
maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
} else
minb = 0;
out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
}
out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
/*
* fix environment for field updated units
*/
if (getenv("altbootcmd") == NULL) {
setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
setenv("usbargs", CONFIG_SYS_USB_ARGS);
setenv("bootcmd", CONFIG_BOOTCOMMAND);
setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
saveenv();
}
return (0);
}
static int ppc4xx_pic_get_irq(void)
{
u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
return uic0 ? 32 - ffs(uic0) : -1;
}
int board_early_init_f(void)
{
register uint reg;
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
mtebc(pb2ap, 0x04814500);
/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
mtebc(pb3ap, 0x00000000);
mtebc(pb3cr, 0x00000000);
mtebc(pb4ap, 0x00000000);
mtebc(pb4cr, 0x00000000);
mtebc(pb5ap, 0x00000000);
mtebc(pb5cr, 0x00000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/*CPLD cs */
/*setup Address lines for flash sizes larger than 16Meg. */
out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
/*setup emac */
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
/*UART1 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
/*clear tmrclk divisor */
*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
/*enable ethernet */
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
/*get rid of flash write protect */
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
return 0;
}
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
int size_val = 0;
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
base_b0 = FLASH_BASE0_PRELIM;
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 << 20);
}
base_b1 = FLASH_BASE1_PRELIM;
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr (EBC0_CFGADDR, PB0CR);
pbcr = mfdcr (EBC0_CFGDATA);
mtdcr (EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
switch (size_b1) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17);
mtdcr (EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0) {
mtdcr (EBC0_CFGADDR, PB1CR);
pbcr = mfdcr (EBC0_CFGDATA);
mtdcr (EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
switch (size_b1) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr (EBC0_CFGDATA, pbcr);
/* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
flash_get_offsets (base_b0, &flash_info[0]);
/* monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
base_b0 + size_b0 - monitor_flash_len,
base_b0 + size_b0 - 1, &flash_info[0]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
flash_get_offsets (base_b1, &flash_info[1]);
/* monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
base_b1 + size_b1 - monitor_flash_len,
base_b1 + size_b1 - 1, &flash_info[1]);
/* monitor protection OFF by default (one is enough) */
flash_protect (FLAG_PROTECT_CLEAR,
base_b0 + size_b0 - monitor_flash_len,
base_b0 + size_b0 - 1, &flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
return (size_b0 + size_b1);
}
int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_8xx)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
volatile sit8xx_t *timers = &immap->im_sit;
/* Hopefully more PowerPC knowledgable people will add code to display
* other useful registers
*/
printf ("\nSystem Configuration registers\n"
"\tIMMR\t0x%08X\n", get_immr(0));
printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
printf("\tSWT\t0x%08X", sysconf->sc_swt);
printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
sysconf->sc_sipend, sysconf->sc_simask);
printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
sysconf->sc_siel, sysconf->sc_sivec);
printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
sysconf->sc_tesr, sysconf->sc_sdcr);
printf ("Memory Controller Registers\n"
"\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
printf ("\n"
"\tmamr\t0x%08X\tmbmr\t0x%08X \n",
memctl->memc_mamr, memctl->memc_mbmr );
printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
memctl->memc_mstat, memctl->memc_mptpr );
printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
printf ("\nSystem Integration Timers\n"
"\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
timers->sit_tbscr, timers->sit_rtcsc);
printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
/*
* May be some CPM info here?
*/
#elif defined (CONFIG_405GP)
printf ("\n405GP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
"uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"\n"
"%08x %08x %08x %08x %08x %08x %08x %08x\n",
mfdcr(uicsr),
mfdcr(uicer),
mfdcr(uiccr),
mfdcr(uicpr),
mfdcr(uictr),
mfdcr(uicmsr),
mfdcr(uicvr),
mfdcr(uicvcr));
puts ("\nMemory (SDRAM) Configuration\n"
"besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
puts ("\n"
"mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd));
printf ("\n\n"
"DMA Channels\n"
"dmasr dmasgc dmaadr\n"
"%08x %08x %08x\n"
"dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n"
"%08x %08x %08x %08x %08x\n"
"dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n"
"%08x %08x %08x %08x %08x\n",
mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
printf (
"dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
"dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
puts ("\n"
"External Bus\n"
"pbear pbesr0 pbesr1 epcr\n");
mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
puts ("\n"
"pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
puts ("\n"
"pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n");
mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd));
puts ("\n\n");
#elif defined(CONFIG_405EP)
printf ("\n405EP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
"uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"\n"
"%08x %08x %08x %08x %08x %08x %08x %08x\n",
mfdcr(uicsr),
mfdcr(uicer),
mfdcr(uiccr),
mfdcr(uicpr),
mfdcr(uictr),
mfdcr(uicmsr),
mfdcr(uicvr),
mfdcr(uicvcr));
puts ("\nMemory (SDRAM) Configuration\n"
"mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
printf ("\n\n"
"DMA Channels\n"
"dmasr dmasgc dmaadr\n" "%08x %08x %08x\n"
"dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
"dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
printf (
"dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
"dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
puts ("\n"
"External Bus\n"
"pbear pbesr0 pbesr1 epcr\n");
mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
puts ("\n"
"pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
puts ("\n"
"pb4cr pb4ap\n");
mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
puts ("\n\n");
#elif defined(CONFIG_5xx)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl5xx_t *memctl = &immap->im_memctl;
volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
volatile sit5xx_t *timers = &immap->im_sit;
volatile car5xx_t *car = &immap->im_clkrst;
volatile uimb5xx_t *uimb = &immap->im_uimb;
puts ("\nSystem Configuration registers\n");
printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
puts ("\nMemory Controller Registers\n");
printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
puts ("\nSystem Integration Timers\n");
printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
puts ("\nClocks and Reset\n");
printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
puts ("\nU-Bus to IMB3 Bus Interface\n");
printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
puts ("\n\n");
#elif defined(CONFIG_MPC5200)
puts ("\nMPC5200 registers\n");
printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
puts ("Memory map registers\n");
printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
*(volatile ulong*)MPC5XXX_CS0_START,
*(volatile ulong*)MPC5XXX_CS0_STOP,
*(volatile ulong*)MPC5XXX_CS0_CFG,
(*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
*(volatile ulong*)MPC5XXX_CS1_START,
*(volatile ulong*)MPC5XXX_CS1_STOP,
*(volatile ulong*)MPC5XXX_CS1_CFG,
(*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
*(volatile ulong*)MPC5XXX_CS2_START,
*(volatile ulong*)MPC5XXX_CS2_STOP,
*(volatile ulong*)MPC5XXX_CS2_CFG,
(*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
*(volatile ulong*)MPC5XXX_CS3_START,
*(volatile ulong*)MPC5XXX_CS3_STOP,
*(volatile ulong*)MPC5XXX_CS3_CFG,
(*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
*(volatile ulong*)MPC5XXX_CS4_START,
*(volatile ulong*)MPC5XXX_CS4_STOP,
*(volatile ulong*)MPC5XXX_CS4_CFG,
(*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
*(volatile ulong*)MPC5XXX_CS5_START,
*(volatile ulong*)MPC5XXX_CS5_STOP,
*(volatile ulong*)MPC5XXX_CS5_CFG,
(*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
*(volatile ulong*)MPC5XXX_CS6_START,
*(volatile ulong*)MPC5XXX_CS6_STOP,
*(volatile ulong*)MPC5XXX_CS6_CFG,
(*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
*(volatile ulong*)MPC5XXX_CS7_START,
*(volatile ulong*)MPC5XXX_CS7_STOP,
*(volatile ulong*)MPC5XXX_CS7_CFG,
(*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
*(volatile ulong*)MPC5XXX_BOOTCS_START,
*(volatile ulong*)MPC5XXX_BOOTCS_STOP,
*(volatile ulong*)MPC5XXX_BOOTCS_CFG,
(*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
printf ("\tSDRAMCS0: %08lX\n",
*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
printf ("\tSDRAMCS1: %08lX\n",
*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
#elif defined(CONFIG_MPC86xx)
mpc86xx_reginfo();
#elif defined(CONFIG_BLACKFIN)
puts("\nSystem Configuration registers\n");
puts("\nPLL Registers\n");
printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n",
bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL());
puts("\nEBIU AMC Registers\n");
printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL());
printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n",
bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
# ifdef EBIU_MODE
printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n",
bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n",
bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
# endif
# ifdef EBIU_RSTCTL
puts("\nEBIU DDR Registers\n");
printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n",
bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n",
bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n",
bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n",
bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
# else
puts("\nEBIU SDC Registers\n");
printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n",
bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
# endif
#endif /* CONFIG_BLACKFIN */
return 0;
}
int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
unsigned int inst, int *advance)
{
int emulated = EMULATE_DONE;
int dcrn;
int ra;
int rb;
int rc;
int rs;
int rt;
int ws;
switch (get_op(inst)) {
case 31:
switch (get_xop(inst)) {
case XOP_MFDCR:
dcrn = get_dcrn(inst);
rt = get_rt(inst);
/* The guest may access CPR0 registers to determine the timebase
* frequency, and it must know the real host frequency because it
* can directly access the timebase registers.
*
* It would be possible to emulate those accesses in userspace,
* but userspace can really only figure out the end frequency.
* We could decompose that into the factors that compute it, but
* that's tricky math, and it's easier to just report the real
* CPR0 values.
*/
switch (dcrn) {
case DCRN_CPR0_CONFIG_ADDR:
kvmppc_set_gpr(vcpu, rt, vcpu->arch.cpr0_cfgaddr);
break;
case DCRN_CPR0_CONFIG_DATA:
local_irq_disable();
mtdcr(DCRN_CPR0_CONFIG_ADDR,
vcpu->arch.cpr0_cfgaddr);
kvmppc_set_gpr(vcpu, rt,
mfdcr(DCRN_CPR0_CONFIG_DATA));
local_irq_enable();
break;
default:
run->dcr.dcrn = dcrn;
run->dcr.data = 0;
run->dcr.is_write = 0;
vcpu->arch.io_gpr = rt;
vcpu->arch.dcr_needed = 1;
kvmppc_account_exit(vcpu, DCR_EXITS);
emulated = EMULATE_DO_DCR;
}
break;
case XOP_MTDCR:
dcrn = get_dcrn(inst);
rs = get_rs(inst);
/* emulate some access in kernel */
switch (dcrn) {
case DCRN_CPR0_CONFIG_ADDR:
vcpu->arch.cpr0_cfgaddr = kvmppc_get_gpr(vcpu, rs);
break;
default:
run->dcr.dcrn = dcrn;
run->dcr.data = kvmppc_get_gpr(vcpu, rs);
run->dcr.is_write = 1;
vcpu->arch.dcr_needed = 1;
kvmppc_account_exit(vcpu, DCR_EXITS);
emulated = EMULATE_DO_DCR;
}
break;
case XOP_TLBWE:
ra = get_ra(inst);
rs = get_rs(inst);
ws = get_ws(inst);
emulated = kvmppc_44x_emul_tlbwe(vcpu, ra, rs, ws);
break;
case XOP_TLBSX:
rt = get_rt(inst);
ra = get_ra(inst);
rb = get_rb(inst);
rc = get_rc(inst);
emulated = kvmppc_44x_emul_tlbsx(vcpu, rt, ra, rb, rc);
break;
case XOP_ICCCI:
break;
default:
emulated = EMULATE_FAIL;
}
break;
default:
emulated = EMULATE_FAIL;
}
if (emulated == EMULATE_FAIL)
emulated = kvmppc_booke_emulate_op(run, vcpu, inst, advance);
return emulated;
}
unsigned long flash_init (void)
{
#ifdef __DEBUG_START_FROM_SRAM__
return CFG_DUMMY_FLASH_SIZE;
#else
unsigned long size_b0;
int i;
uint pbcr;
unsigned long base_b0;
int size_val = 0;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Setup offsets */
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
mtdcr(ebccfgd, pbcr);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
flash_info[0].size = size_b0;
return (size_b0);
#endif
}
unsigned long flash_init(void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 =
flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 << 20);
}
/* Only one bank */
if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
/* Setup offsets */
flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
&flash_info[0]);
#ifdef CONFIG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
size_b1 = 0;
flash_info[0].size = size_b0;
} else {
/* 2 banks */
size_b1 =
flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
&flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
pbcr =
(pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0) {
mtdcr(EBC0_CFGADDR, PB1CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
pbcr =
(pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
flash_get_offsets(base_b0, &flash_info[0]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b0 + size_b0 - monitor_flash_len,
base_b0 + size_b0 - 1, &flash_info[0]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 =
flash_get_size((vu_long *) base_b1, &flash_info[1]);
flash_get_offsets(base_b1, &flash_info[1]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b1 + size_b1 -
monitor_flash_len,
base_b1 + size_b1 - 1,
&flash_info[1]);
/* monitor protection OFF by default (one is enough) */
(void)flash_protect(FLAG_PROTECT_CLEAR,
base_b0 + size_b0 -
monitor_flash_len,
base_b0 + size_b0 - 1,
&flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
} /* else 2 banks */
return (size_b0 + size_b1);
}
/*
* Returns number of bytes left to be transferred from the entire sgl list.
* *src_addr and *dst_addr get set to the source/destination address of
* the sgl descriptor where the DMA stopped.
*
* An sgl transfer must NOT be active when this function is called.
*/
static __inline__ int
ppc4xx_get_dma_sgl_residue(sgl_handle_t handle, phys_addr_t * src_addr,
phys_addr_t * dst_addr)
{
sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
ppc_dma_ch_t *p_dma_ch;
ppc_sgl_t *pnext, *sgl_addr;
uint32_t count_left;
if (!handle) {
printk("ppc4xx_get_dma_sgl_residue: null handle\n");
return DMA_STATUS_BAD_HANDLE;
} else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
printk("ppc4xx_get_dma_sgl_residue: bad channel in handle %d\n",
psgl->dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
switch (psgl->dmanr) {
case 0:
sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG0));
count_left = mfdcr(DCRN_DMACT0);
break;
case 1:
sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG1));
count_left = mfdcr(DCRN_DMACT1);
break;
case 2:
sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG2));
count_left = mfdcr(DCRN_DMACT2);
break;
case 3:
sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG3));
count_left = mfdcr(DCRN_DMACT3);
break;
default:
printk("ppc4xx_get_dma_sgl_residue: bad channel %d\n", psgl->dmanr);
goto error;
}
if (!sgl_addr) {
printk("ppc4xx_get_dma_sgl_residue: sgl addr register is null\n");
goto error;
}
pnext = psgl->phead;
while (pnext &&
((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE) &&
(pnext != sgl_addr))
) {
pnext++;
}
if (pnext == sgl_addr) { /* found the sgl descriptor */
*src_addr = pnext->src_addr;
*dst_addr = pnext->dst_addr;
/*
* Now search the remaining descriptors and add their count.
* We already have the remaining count from this descriptor in
* count_left.
*/
pnext++;
while ((pnext != psgl->ptail) &&
((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE))
) {
count_left += pnext->control_count & SG_COUNT_MASK;
}
if (pnext != psgl->ptail) { /* should never happen */
printk
("ppc4xx_get_dma_sgl_residue error (1) psgl->ptail 0x%x handle 0x%x\n",
(unsigned int) psgl->ptail, (unsigned int) handle);
goto error;
}
/* success */
p_dma_ch = &dma_channels[psgl->dmanr];
return (count_left << p_dma_ch->shift); /* count in bytes */
} else {
/* this shouldn't happen */
printk
("get_dma_sgl_residue, unable to match current address 0x%x, handle 0x%x\n",
(unsigned int) sgl_addr, (unsigned int) handle);
}
error:
*src_addr = (phys_addr_t) NULL;
*dst_addr = (phys_addr_t) NULL;
return 0;
}
int
ppc4xx_get_dma_status(void)
{
return (mfdcr(DCRN_DMASR));
}
void
ppc4xx_find_bridges(void)
{
struct pci_controller *hose_a;
struct pcil0_regs *pcip;
unsigned int new_pmm_max;
unsigned int new_pmm_min;
isa_io_base = 0;
isa_mem_base = 0;
pci_dram_offset = 0;
#if (PSR_PCI_ARBIT_EN > 1)
/* Check if running in slave mode */
if ((mfdcr(DCRN_CHPSR) & PSR_PCI_ARBIT_EN) == 0) {
printk("Running as PCI slave, kernel PCI disabled !\n");
return;
}
#endif
/* Setup PCI32 hose */
hose_a = pcibios_alloc_controller();
if (!hose_a)
return;
setup_indirect_pci(hose_a, PPC405_PCI_CONFIG_ADDR,
PPC405_PCI_CONFIG_DATA);
#ifdef CONFIG_XILINX_OCP
/* Eliminate "unused variable" warning for pcip. Optimizer removes. */
pcip = NULL;
new_pmm_min = PPC405_PCI_LOWER_MEM;
new_pmm_max = PPC405_PCI_UPPER_MEM;
#else /* Must be IBM */
pcip = ioremap(PPC4xx_PCI_LCFG_PADDR, PAGE_SIZE);
if (pcip != NULL) {
unsigned int tmp_addr;
unsigned int tmp_size;
unsigned int reg_index;
#if defined(CONFIG_BIOS_FIXUP)
bios_fixup(hose_a, pcip);
#endif
new_pmm_min = 0xffffffff;
for (reg_index = 0; reg_index < 3; reg_index++) {
tmp_size = in_le32((void *) &(pcip->pmm[reg_index].ma)); // *_PMM0MA
if (tmp_size & 0x1) {
tmp_addr = in_le32((void *) &(pcip->pmm[reg_index].pcila)); // *_PMM0PCILA
if (tmp_addr < PPC405_PCI_PHY_MEM_BASE) {
printk(KERN_DEBUG
"Disabling mapping to PCI mem addr 0x%8.8x\n",
tmp_addr);
out_le32((void *) &(pcip->pmm[reg_index].ma), tmp_size & ~1); // *_PMMOMA
} else {
tmp_addr = in_le32((void *) &(pcip->pmm[reg_index].la)); // *_PMMOLA
if (tmp_addr < new_pmm_min)
new_pmm_min = tmp_addr;
tmp_addr =
tmp_addr + (0xffffffff -
(tmp_size &
0xffffc000));
if (tmp_addr > PPC405_PCI_UPPER_MEM) {
new_pmm_max = tmp_addr; // PPC405_PCI_UPPER_MEM
} else {
new_pmm_max =
PPC405_PCI_UPPER_MEM;
}
}
}
} // for
iounmap(pcip);
}
#endif
hose_a->first_busno = 0;
hose_a->last_busno = 0xff;
hose_a->pci_mem_offset = 0;
/* Setup bridge memory/IO ranges & resources
* TODO: Handle firmwares setting up a legacy ISA mem base
*/
hose_a->io_space.start = PPC405_PCI_LOWER_IO;
hose_a->io_space.end = PPC405_PCI_UPPER_IO;
hose_a->mem_space.start = new_pmm_min;
hose_a->mem_space.end = new_pmm_max;
hose_a->io_base_phys = PPC405_PCI_PHY_IO_BASE;
hose_a->io_base_virt = ioremap(hose_a->io_base_phys, 0x10000);
hose_a->io_resource.start = 0;
hose_a->io_resource.end = PPC405_PCI_UPPER_IO - PPC405_PCI_LOWER_IO;
hose_a->io_resource.flags = IORESOURCE_IO;
hose_a->io_resource.name = "PCI I/O";
hose_a->mem_resources[0].start = new_pmm_min;
hose_a->mem_resources[0].end = new_pmm_max;
hose_a->mem_resources[0].flags = IORESOURCE_MEM;
hose_a->mem_resources[0].name = "PCI Memory";
isa_io_base = (int) hose_a->io_base_virt;
isa_mem_base = 0; /* ISA not implemented */
ISA_DMA_THRESHOLD = 0x00ffffff; /* ??? ISA not implemented */
/* Scan busses & initial setup by pci_auto */
hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
/* Setup ppc_md */
ppc_md.pcibios_fixup = NULL;
ppc_md.pci_exclude_device = ppc4xx_exclude_device;
ppc_md.pcibios_fixup_resources = ppc405_pcibios_fixup_resources;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = ppc405_map_irq;
}
/*
* Configures a DMA channel, including the peripheral bus width, if a
* peripheral is attached to the channel, the polarity of the DMAReq and
* DMAAck signals, etc. This information should really be setup by the boot
* code, since most likely the configuration won't change dynamically.
* If the kernel has to call this function, it's recommended that it's
* called from platform specific init code. The driver should not need to
* call this function.
*/
int
ppc4xx_init_dma_channel(unsigned int dmanr, ppc_dma_ch_t * p_init)
{
unsigned int polarity;
uint32_t control = 0;
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
DMA_MODE_READ = (unsigned long) DMA_TD; /* Peripheral to Memory */
DMA_MODE_WRITE = 0; /* Memory to Peripheral */
if (!p_init) {
printk("ppc4xx_init_dma_channel: NULL p_init\n");
return DMA_STATUS_NULL_POINTER;
}
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_init_dma_channel: bad channel %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
#if DCRN_POL > 0
polarity = mfdcr(DCRN_POL);
#else
polarity = 0;
#endif
/* Setup the control register based on the values passed to
* us in p_init. Then, over-write the control register with this
* new value.
*/
control |= SET_DMA_CONTROL;
/* clear all polarity signals and then "or" in new signal levels */
polarity &= ~GET_DMA_POLARITY(dmanr);
polarity |= p_dma_ch->polarity;
#if DCRN_POL > 0
mtdcr(DCRN_POL, polarity);
#endif
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
/* save these values in our dma channel structure */
memcpy(p_dma_ch, p_init, sizeof (ppc_dma_ch_t));
/*
* The peripheral width values written in the control register are:
* PW_8 0
* PW_16 1
* PW_32 2
* PW_64 3
*
* Since the DMA count register takes the number of "transfers",
* we need to divide the count sent to us in certain
* functions by the appropriate number. It so happens that our
* right shift value is equal to the peripheral width value.
*/
p_dma_ch->shift = p_init->pwidth;
/*
* Save the control word for easy access.
*/
p_dma_ch->control = control;
mtdcr(DCRN_DMASR, 0xffffffff); /* clear status register */
return DMA_STATUS_GOOD;
}