static void mt7628_ephy_init(void)
{
int i;
u32 val;
val = sysRegRead(REG_AGPIOCFG);
val &= ~(MT7628_P0_EPHY_AIO_EN | MT7628_P1_EPHY_AIO_EN | MT7628_P2_EPHY_AIO_EN | MT7628_P3_EPHY_AIO_EN | MT7628_P4_EPHY_AIO_EN);
sysRegWrite(REG_AGPIOCFG, val);
// reset EPHY
esw_ephy_reset();
udelay(5000);
/* set P0~P4 EPHY LED mode */
sysRegRead(RALINK_SYSCTL_BASE + 0x64);
val &= 0xf003f003;
sysRegWrite(RALINK_SYSCTL_BASE + 0x64, val);
mii_mgr_write(0, 31, 0x2000); // change G2 page
mii_mgr_write(0, 26, 0x0000);
for(i=0; i<5; i++) {
mii_mgr_write(i, 31, 0x8000); // change L0 page
mii_mgr_write(i, 0, 0x3100);
#if defined (CONFIG_RAETH_8023AZ_EEE)
mii_mgr_read(i, 26, &phy_val); // EEE setting
phy_val |= (1 << 5);
mii_mgr_write(i, 26, phy_val);
#endif
mii_mgr_write(i, 30, 0xa000);
mii_mgr_write(i, 31, 0xa000); // change L2 page
mii_mgr_write(i, 16, 0x0606);
mii_mgr_write(i, 23, 0x0f0e);
mii_mgr_write(i, 24, 0x1610);
mii_mgr_write(i, 30, 0x1f15);
mii_mgr_write(i, 28, 0x6111);
#if 0
mii_mgr_read(i, 4, &phy_val);
phy_val |= (1 << 10);
mii_mgr_write(i, 4, phy_val);
mii_mgr_write(i, 31, 0x2000); // change G2 page
mii_mgr_write(i, 26, 0x0000);
#endif
}
//100Base AOI setting
mii_mgr_write(0, 31, 0x5000); //change G5 page
mii_mgr_write(0, 19, 0x004a);
mii_mgr_write(0, 20, 0x015a);
mii_mgr_write(0, 21, 0x00ee);
mii_mgr_write(0, 22, 0x0033);
mii_mgr_write(0, 23, 0x020a);
mii_mgr_write(0, 24, 0x0000);
mii_mgr_write(0, 25, 0x024a);
mii_mgr_write(0, 26, 0x035a);
mii_mgr_write(0, 27, 0x02ee);
mii_mgr_write(0, 28, 0x0233);
mii_mgr_write(0, 29, 0x000a);
mii_mgr_write(0, 30, 0x0000);
}
int smi_read(u32 addr, u32 *data)
{
spin_lock(&g_mdio_lock);
/* Write Start command to register 29 */
mii_mgr_write(g_phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
/* Write address control code to register 31 */
mii_mgr_write(g_phy_id, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);
/* Write Start command to register 29 */
mii_mgr_write(g_phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
/* Write address to register 23 */
mii_mgr_write(g_phy_id, MDC_MDIO_ADDRESS_REG, addr);
/* Write Start command to register 29 */
mii_mgr_write(g_phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
/* Write read control code to register 21 */
mii_mgr_write(g_phy_id, MDC_MDIO_CTRL1_REG, MDC_MDIO_READ_OP);
/* Write Start command to register 29 */
mii_mgr_write(g_phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);
/* Read data from register 25 */
mii_mgr_read(g_phy_id, MDC_MDIO_DATA_READ_REG, data);
spin_unlock(&g_mdio_lock);
return RT_ERR_OK;
}
static int et_virt_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
int mdio_cfg_reg;
int mii_an_reg;
PSEUDO_ADAPTER *pseudo = dev->priv;
//printk("et_set_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause);
// auto-neg pause
mii_mgr_read(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg);
if(epause->autoneg)
mii_an_reg |= AN_PAUSE;
else
mii_an_reg &= ~AN_PAUSE;
mii_mgr_write(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, mii_an_reg);
// tx/rx pause
mdio_cfg_reg = sysRegRead(MDIO_CFG);
if(epause->tx_pause)
mdio_cfg_reg |= MDIO_CFG_GP1_FC_TX;
else
mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_TX;
if(epause->rx_pause)
mdio_cfg_reg |= MDIO_CFG_GP1_FC_RX;
else
mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_RX;
sysRegWrite(MDIO_CFG, mdio_cfg_reg);
return 0;
}
void ext_gphy_eee_enable(u32 phy_addr, int is_eee_enabled)
{
u32 phy_id0 = 0, phy_id1 = 0, phy_rev;
if (!mii_mgr_read(phy_addr, 2, &phy_id0))
return;
if (!mii_mgr_read(phy_addr, 3, &phy_id1))
return;
phy_rev = phy_id1 & 0xf;
if ((phy_id0 == EV_REALTEK_PHY_ID0) && ((phy_id1 & 0xfff0) == EV_REALTEK_PHY_ID1)) {
if (phy_rev >= 0x4) {
/* EEE LPI 1000/100 advert (for D/E/F) */
mii_mgr_write_cl45(phy_addr, 0x07, 0x003c, (is_eee_enabled) ? 0x0006 : 0x0000);
}
}
}
int mdio_virt_read(struct net_device *dev, int phy_id, int location)
{
unsigned int result;
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
PSEUDO_ADAPTER *pseudo = netdev_priv(dev);
#else
PSEUDO_ADAPTER *pseudo = dev->priv;
#endif
mii_mgr_read( (unsigned int) pseudo->mii_info.phy_id, (unsigned int)location, &result);
// printk("%s mii.o query= phy_id:%d, address:%d retval:%d\n", dev->name, phy_id, location, result);
return (int)result;
}
/*
* mii_mgr_read wrapper for mii.o ethtool
*/
int mdio_read(struct net_device *dev, int phy_id, int location)
{
unsigned int result;
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
END_DEVICE *ei_local = netdev_priv(dev);
#else
END_DEVICE *ei_local = dev->priv;
#endif
mii_mgr_read( (unsigned int) ei_local->mii_info.phy_id, (unsigned int)location, &result);
//printk("\n%s mii.o query= phy_id:%d, address:%d retval:%x\n", dev->name, phy_id, location, result);
return (int)result;
}
/* called once on driver load */
void early_phy_init(void)
{
#if defined (CONFIG_RAETH_ESW) || defined (CONFIG_MT7530_GSW)
#if defined (CONFIG_P5_MAC_TO_PHY_MODE) || defined (CONFIG_GE2_RGMII_AN)
#define MAX_PHY_NUM 6
#else
#define MAX_PHY_NUM 5
#endif
u32 i, phy_mdio_addr, phy_reg_mcr;
#endif
#if defined (CONFIG_P5_MAC_TO_PHY_MODE) || defined (CONFIG_GE1_RGMII_AN) || \
defined (CONFIG_P4_MAC_TO_PHY_MODE) || defined (CONFIG_GE2_RGMII_AN) || \
defined (CONFIG_MT7530_GSW)
/* enable MDIO port */
mii_mgr_init();
#endif
#if defined (CONFIG_RAETH_ESW) || defined (CONFIG_MT7530_GSW)
/* early down all switch PHY (please enable from user-level) */
for (i = 0; i < MAX_PHY_NUM; i++) {
phy_mdio_addr = i;
#if defined (CONFIG_P4_MAC_TO_PHY_MODE)
if (i == 4)
phy_mdio_addr = CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2;
#endif
#if defined (CONFIG_P5_MAC_TO_PHY_MODE)
if (i == 5)
phy_mdio_addr = CONFIG_MAC_TO_GIGAPHY_MODE_ADDR;
#elif defined (CONFIG_GE2_RGMII_AN)
if (i == 5)
phy_mdio_addr = CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2;
#endif
phy_reg_mcr = 0x3100;
if (mii_mgr_read(phy_mdio_addr, 0, &phy_reg_mcr)) {
if (phy_reg_mcr & (1<<11))
continue;
phy_reg_mcr &= ~(1<<9);
phy_reg_mcr |= ((1<<12)|(1<<11));
mii_mgr_write(phy_mdio_addr, 0, phy_reg_mcr);
}
}
#endif
#if defined (CONFIG_MT7530_GSW)
/* early P5/P6 MAC link down */
mii_mgr_write(MT7530_MDIO_ADDR, 0x3500, 0x8000);
mii_mgr_write(MT7530_MDIO_ADDR, 0x3600, 0x8000);
#endif
}
static void et_virt_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
int mii_an_reg, mdio_cfg_reg;
PSEUDO_ADAPTER *pseudo = dev->priv;
// get mii auto-negotiation register
mii_mgr_read(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg);
epause->autoneg = (mii_an_reg & AN_PAUSE) ? 1 : 0; //get autonet_enable flag bit
mdio_cfg_reg = sysRegRead(MDIO_CFG);
epause->tx_pause = (mdio_cfg_reg & MDIO_CFG_GP1_FC_TX) ? 1 : 0;
epause->rx_pause = (mdio_cfg_reg & MDIO_CFG_GP1_FC_RX) ? 1 : 0;
//printk("et_get_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause);
}
static void rt5350_ephy_init(void)
{
int i;
u32 phy_val;
// reset EPHY
esw_ephy_reset();
//select local register
mii_mgr_write(0, 31, 0x8000);
for(i=0; i<5; i++) {
mii_mgr_write(i, 26, 0x1600); //TX10 waveform coefficient //LSB=0 disable PHY
mii_mgr_write(i, 29, 0x7015); //TX100/TX10 AD/DA current bias
mii_mgr_write(i, 30, 0x0038); //TX100 slew rate control
}
//select global register
mii_mgr_write(0, 31, 0x0);
mii_mgr_write(0, 1, 0x4a40); //enlarge agcsel threshold 3 and threshold 2
mii_mgr_write(0, 2, 0x6254); //enlarge agcsel threshold 5 and threshold 4
mii_mgr_write(0, 3, 0xa17f); //enlarge agcsel threshold 6
mii_mgr_write(0, 12, 0x7eaa);
mii_mgr_write(0, 14, 0x65); //longer TP_IDL tail length
mii_mgr_write(0, 16, 0x0684); //increased squelch pulse count threshold.
mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum
mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold
mii_mgr_write(0, 22, 0x253f); //tune TP_IDL tail and head waveform, enable power down slew rate control
mii_mgr_write(0, 27, 0x2fda); //set PLL/Receive bias current are calibrated
mii_mgr_write(0, 28, 0xc410); //change PLL/Receive bias current to internal(RT3350)
mii_mgr_write(0, 29, 0x598b); //change PLL bias current to internal(RT3052_MP3)
mii_mgr_write(0, 31, 0x8000); //select local register
for(i=0; i<5; i++) {
//LSB=1 enable PHY
mii_mgr_read(i, 26, &phy_val);
phy_val |= 0x0001;
mii_mgr_write(i, 26, phy_val);
}
}
void ext_gphy_init(u32 phy_addr)
{
const char *phy_devn = NULL;
u32 phy_id0 = 0, phy_id1 = 0, phy_val = 0, phy_rev;
if (!mii_mgr_read(phy_addr, 2, &phy_id0))
return;
if (!mii_mgr_read(phy_addr, 3, &phy_id1))
return;
phy_rev = phy_id1 & 0xf;
if ((phy_id0 == EV_ICPLUS_PHY_ID0) && ((phy_id1 & 0xfff0) == EV_ICPLUS_PHY_ID1)) {
phy_devn = "IC+ IP1001";
mii_mgr_read(phy_addr, 4, &phy_val);
phy_val |= (1<<10); // enable pause ability
mii_mgr_write(phy_addr, 4, phy_val);
mii_mgr_read(phy_addr, 0, &phy_val);
if (!(phy_val & (1<<11))) {
phy_val |= (1<<9); // restart AN
mii_mgr_write(phy_addr, 0, phy_val);
}
} else
if ((phy_id0 == EV_REALTEK_PHY_ID0) && ((phy_id1 & 0xfff0) == EV_REALTEK_PHY_ID1)) {
phy_devn = "RTL8211";
if (phy_rev == 0x6) {
phy_devn = "RTL8211F";
/* Disable response on MDIO addr 0 (!) */
mii_mgr_read(phy_addr, 24, &phy_val);
phy_val &= ~(1<<13); // PHYAD_0 Disable
mii_mgr_write(phy_addr, 24, phy_val);
/* set RGMII mode */
mii_mgr_write(phy_addr, 31, 0x0d08);
mii_mgr_read(phy_addr, 17, &phy_val);
phy_val |= (1<<8); // enable TXDLY
mii_mgr_write(phy_addr, 17, phy_val);
mii_mgr_write(phy_addr, 31, 0x0000);
/* Disable Green Ethernet */
mii_mgr_write(phy_addr, 27, 0x8011);
mii_mgr_write(phy_addr, 28, 0x573f);
} else if (phy_rev == 0x5) {
phy_devn = "RTL8211E";
/* Disable Green Ethernet */
mii_mgr_write(phy_addr, 31, 0x0003);
mii_mgr_write(phy_addr, 25, 0x3246);
mii_mgr_write(phy_addr, 16, 0xa87c);
mii_mgr_write(phy_addr, 31, 0x0000);
}
if (phy_rev >= 0x4) {
/* disable EEE LPI 1000/100 advert (for D/E/F) */
mii_mgr_write_cl45(phy_addr, 0x07, 0x003c, 0x0000);
}
} else
if ((phy_id0 == EV_MARVELL_PHY_ID0) && (phy_id1 == EV_MARVELL_PHY_ID1)) {
phy_devn = "Marvell";
mii_mgr_read(phy_addr, 20, &phy_val);
phy_val |= (1<<7); // add delay to RX_CLK for RXD Outputs
mii_mgr_write(phy_addr, 20, phy_val);
mii_mgr_read(phy_addr, 0, &phy_val);
phy_val |= (1<<15); // PHY Software Reset
mii_mgr_write(phy_addr, 0, phy_val);
} else
if ((phy_id0 == EV_VTSS_PHY_ID0) && (phy_id1 == EV_VTSS_PHY_ID1)) {
phy_devn = "Vitesse VSC8601";
mii_mgr_write(phy_addr, 31, 0x0001); // extended page
mii_mgr_read(phy_addr, 28, &phy_val);
phy_val |= (0x3<<12); // RGMII RX skew compensation= 2.0 ns
phy_val &= ~(0x3<<14); // RGMII TX skew compensation= 0 ns
mii_mgr_write(phy_addr, 28, phy_val);
mii_mgr_write(phy_addr, 31, 0x0000); // main registers
}
if (phy_devn)
printk("%s GPHY detected on MDIO addr 0x%02X\n", phy_devn, phy_addr);
else
printk("Unknown EPHY (%04X:%04X) detected on MDIO addr 0x%02X\n",
phy_id0, phy_id1, phy_addr);
}
/* external GSW MT7350 */
void mt7530_gsw_init(void)
{
u32 i, regValue = 0;
/* configure MT7530 HW-TRAP */
mii_mgr_read(MT7530_MDIO_ADDR, 0x7804, ®Value);
regValue |= (1<<16); // Change HW-TRAP
regValue |= (1<<24); // Standalone Switch
regValue &= ~(1<<8); // Enable Port 6
#if defined (CONFIG_P4_RGMII_TO_MT7530_GMAC_P5)
regValue &= ~((1<<6)|(1<<5)|(1<<15)); // Enable Port5
regValue |= ((1<<13)|(1<<7)); // Port 5 as GMAC, no Internal PHY mode
#elif defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P0)
regValue &= ~((1<<6)|(1<<5)|(1<<15)|(1<<13)); // Enable Port5, set to PHY P0 mode
regValue |= ((1<<7)|(1<<20));
#elif defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P4)
regValue &= ~((1<<6)|(1<<5)|(1<<15)|(1<<13)|(1<<20)); // Enable Port5, set to PHY P4 mode
regValue |= ((1<<7));
#else
regValue |= ((1<<6)|(1<<13)); // Disable Port 5, set as GMAC, no Internal PHY mode
#endif
mii_mgr_write(MT7530_MDIO_ADDR, 0x7804, regValue);
/* configure MT7530 Port6 */
#if defined (CONFIG_P4_RGMII_TO_MT7530_GMAC_P5)
/* do not override P6 security (use external switch control) */
#elif defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P4)
mii_mgr_write(MT7530_MDIO_ADDR, 0x2604, 0x004f0000); // P6 has matrix mode (P6|P3|P2|P1|P0)
mii_mgr_write(MT7530_MDIO_ADDR, 0x2610, 0x810000c0); // P6 is transparent port, admit all frames
#elif defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P0)
mii_mgr_write(MT7530_MDIO_ADDR, 0x2604, 0x005e0000); // P6 has matrix mode (P6|P4|P3|P2|P1)
mii_mgr_write(MT7530_MDIO_ADDR, 0x2610, 0x810000c0); // P6 is transparent port, admit all frames
#else
mii_mgr_write(MT7530_MDIO_ADDR, 0x2604, 0x205f0003); // P6 set security mode, egress always tagged
mii_mgr_write(MT7530_MDIO_ADDR, 0x2610, 0x81000000); // P6 is user port, admit all frames
#endif
mii_mgr_write(MT7530_MDIO_ADDR, 0x3600, 0x0005e33b); // (P6, Force mode, Link Up, 1000Mbps, Full-Duplex, FC ON)
/* configure MT7530 Port5 */
#if defined (CONFIG_P4_RGMII_TO_MT7530_GMAC_P5)
/* do not override P5 security (use external switch control) */
mii_mgr_write(MT7530_MDIO_ADDR, 0x3500, 0x0005e33b); // (P5, Force mode, Link Up, 1000Mbps, Full-Duplex, FC ON)
#elif defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P4) || defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P0)
mii_mgr_write(MT7530_MDIO_ADDR, 0x3500, 0x00056300); // (P5, AN) ???
#endif
/* set MT7530 central align */
mii_mgr_read(MT7530_MDIO_ADDR, 0x7830, ®Value);
regValue &= ~1;
regValue |= (1<<1);
mii_mgr_write(MT7530_MDIO_ADDR, 0x7830, regValue);
mii_mgr_read(MT7530_MDIO_ADDR, 0x7a40, ®Value);
regValue &= ~(1<<30);
mii_mgr_write(MT7530_MDIO_ADDR, 0x7a40, regValue);
mii_mgr_write(MT7530_MDIO_ADDR, 0x7a78, 0x855);
#if defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P4) || defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P0)
/* set MT7530 delay setting for 10/1000M */
mii_mgr_write(MT7530_MDIO_ADDR, 0x7b00, 0x102);
mii_mgr_write(MT7530_MDIO_ADDR, 0x7b04, 0x14);
#endif
/* enable switch INTR */
mii_mgr_read(MT7530_MDIO_ADDR, 0x7808, ®Value);
regValue |= (3<<16);
mii_mgr_write(MT7530_MDIO_ADDR, 0x7808, regValue);
}
/* external GSW MT7350 */
void mt7530_gsw_init(void)
{
u32 i, regValue = 0;
/* turn off all PHY */
for(i = 0; i <= 4; i++) {
mii_mgr_read(i, 0, ®Value);
regValue |= (1<<11);
mii_mgr_write(i, 0, regValue);
}
/* configure MT7530 HW-TRAP */
mii_mgr_read(MT7530_MDIO_ADDR, 0x7804, ®Value);
regValue |= (1<<16); // Change HW-TRAP
regValue |= (1<<24); // Standalone Switch
regValue &= ~(1<<8); // Enable Port 6
#if defined (CONFIG_P4_RGMII_TO_MT7530_GMAC_P5)
regValue &= ~((1<<6)|(1<<5)|(1<<15)); // Enable Port5
regValue |= ((1<<13)|(1<<7)); // Port 5 as GMAC, no Internal PHY mode
#elif defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P0)
regValue &= ~((1<<6)|(1<<5)|(1<<15)|(1<<13)); // Enable Port5, set to PHY P0 mode
regValue |= ((1<<7)|(1<<20));
#elif defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P4)
regValue &= ~((1<<6)|(1<<5)|(1<<15)|(1<<13)|(1<<20)); // Enable Port5, set to PHY P4 mode
regValue |= ((1<<7));
#else
regValue |= ((1<<6)|(1<<13)); // Disable Port 5, set as GMAC, no Internal PHY mode
#endif
mii_mgr_write(MT7530_MDIO_ADDR, 0x7804, regValue);
/* configure MT7530 Port6 */
#if defined (CONFIG_P4_RGMII_TO_MT7530_GMAC_P5)
mii_mgr_write(MT7530_MDIO_ADDR, 0x2604, 0x204f0003); // P6 set security mode, egress always tagged
mii_mgr_write(MT7530_MDIO_ADDR, 0x2610, 0x81000000); // P6 is user port, admit all frames
#elif defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P4)
mii_mgr_write(MT7530_MDIO_ADDR, 0x2604, 0x004f0000); // P6 has matrix mode (P6|P3|P2|P1|P0)
mii_mgr_write(MT7530_MDIO_ADDR, 0x2610, 0x810000c0); // P6 is transparent port, admit all frames
#elif defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P0)
mii_mgr_write(MT7530_MDIO_ADDR, 0x2604, 0x005e0000); // P6 has matrix mode (P6|P4|P3|P2|P1)
mii_mgr_write(MT7530_MDIO_ADDR, 0x2610, 0x810000c0); // P6 is transparent port, admit all frames
#else
mii_mgr_write(MT7530_MDIO_ADDR, 0x2604, 0x205f0003); // P6 set security mode, egress always tagged
mii_mgr_write(MT7530_MDIO_ADDR, 0x2610, 0x81000000); // P6 is user port, admit all frames
#endif
mii_mgr_write(MT7530_MDIO_ADDR, 0x3600, 0x0005e33b); // (P6, Force mode, Link Up, 1000Mbps, Full-Duplex, FC ON)
/* configure MT7530 Port5 */
#if defined (CONFIG_P4_RGMII_TO_MT7530_GMAC_P5)
mii_mgr_write(MT7530_MDIO_ADDR, 0x2504, 0x20300003); // P5 set security mode, egress always tagged
mii_mgr_write(MT7530_MDIO_ADDR, 0x2510, 0x81000000); // P5 is user port, admit all frames
mii_mgr_write(MT7530_MDIO_ADDR, 0x3500, 0x0005e33b); // (P5, Force mode, Link Up, 1000Mbps, Full-Duplex, FC ON)
#elif defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P4) || defined (CONFIG_P4_MAC_TO_MT7530_GPHY_P0)
mii_mgr_write(MT7530_MDIO_ADDR, 0x3500, 0x00056300); // (P5, AN) ???
#endif
/* set MT7530 central align */
mii_mgr_read(MT7530_MDIO_ADDR, 0x7830, ®Value);
regValue &= ~1;
regValue |= (1<<1);
mii_mgr_write(MT7530_MDIO_ADDR, 0x7830, regValue);
mii_mgr_read(MT7530_MDIO_ADDR, 0x7a40, ®Value);
regValue &= ~(1<<30);
mii_mgr_write(MT7530_MDIO_ADDR, 0x7a40, regValue);
regValue = 0x855;
mii_mgr_write(MT7530_MDIO_ADDR, 0x7a78, regValue);
#if 0
/* todo, more documentation is needed */
/* set MT7530 delay setting for 10/1000M */
mii_mgr_write(MT7530_MDIO_ADDR, 0x7b00, 0x102);
mii_mgr_write(MT7530_MDIO_ADDR, 0x7b04, 0x14);
/* disable EEE */
for (i = 0; i <= 4; i++) {
mii_mgr_write(i, 13, 0x7);
mii_mgr_write(i, 14, 0x3C);
mii_mgr_write(i, 13, 0x4007);
mii_mgr_write(i, 14, 0x0);
}
/* disable EEE 10Base-T */
for (i = 0; i <= 4; i++) {
mii_mgr_write(i, 13, 0x1f);
mii_mgr_write(i, 14, 0x027b);
mii_mgr_write(i, 13, 0x401f);
mii_mgr_write(i, 14, 0x1177);
}
#endif
/* enable switch INTR */
mii_mgr_read(MT7530_MDIO_ADDR, 0x7808, ®Value);
regValue |= (3<<16);
mii_mgr_write(MT7530_MDIO_ADDR, 0x7808, regValue);
}