int hieth_mdiobus_driver_init(void) { mdio_bus_ld.iobase_phys = ETH_IO_ADDRESS_BASE; mdio_bus_ld.mdio_frqdiv = ETH_MDIO_FRQDIV; hieth_mdio_init(&mdio_bus_ld); /* UpEther PHY init */ miiphy_register(U_PHY_NAME, hieth_mdiobus_read, hieth_mdiobus_write); if(!get_phy_device(U_PHY_NAME,U_PHY_ADDR)) { miiphy_reset(U_PHY_NAME, U_PHY_ADDR); miiphy_set_current_dev(U_PHY_NAME); } /* DownEther PHY init */ miiphy_register(D_PHY_NAME, hieth_mdiobus_read, hieth_mdiobus_write); if(!get_phy_device(D_PHY_NAME,D_PHY_ADDR)) { miiphy_reset(D_PHY_NAME, D_PHY_ADDR); miiphy_set_current_dev(D_PHY_NAME); } return 0; }
int fec_initialize(bd_t *bis) { struct eth_device* dev; int i; for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) { dev = (struct eth_device*) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); sprintf(dev->name, "FCC%d", ether_fcc_info[i].ether_index + 1); dev->priv = ðer_fcc_info[i]; dev->init = fec_init; dev->halt = fec_halt; dev->send = fec_send; dev->recv = fec_recv; eth_register(dev); #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ && defined(CONFIG_BITBANGMII) miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); #endif } return 1; }
int au1x00_enet_initialize(bd_t *bis){ struct eth_device* dev; if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) { puts ("malloc failed\n"); return -1; } memset(dev, 0, sizeof *dev); sprintf(dev->name, "Au1X00 ethernet"); dev->iobase = 0; dev->priv = 0; dev->init = au1x00_init; dev->halt = au1x00_halt; dev->send = au1x00_send; dev->recv = au1x00_recv; eth_register(dev); #if defined(CONFIG_CMD_MII) miiphy_register(dev->name, au1x00_miiphy_read, au1x00_miiphy_write); #endif return 1; }
int at91rm9200_miiphy_initialize(bd_t *bis) { #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write); #endif return 0; }
int bfin_EMAC_initialize(bd_t *bis) { struct eth_device *dev; dev = malloc(sizeof(*dev)); if (dev == NULL) hang(); memset(dev, 0, sizeof(*dev)); strcpy(dev->name, "bfin_mac"); dev->iobase = 0; dev->priv = 0; dev->init = bfin_EMAC_init; dev->halt = bfin_EMAC_halt; dev->send = bfin_EMAC_send; dev->recv = bfin_EMAC_recv; dev->write_hwaddr = bfin_EMAC_setup_addr; eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write); #endif return 0; }
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) { struct macb_device *macb; struct eth_device *netdev; u32 ncfgr; macb = malloc(sizeof(struct macb_device)); if (!macb) { printf("Error: Failed to allocate memory for MACB%d\n", id); return -1; } memset(macb, 0, sizeof(struct macb_device)); netdev = &macb->netdev; macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE, &macb->rx_buffer_dma); macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc), &macb->rx_ring_dma); macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc), &macb->tx_ring_dma); macb->regs = regs; macb->phy_addr = phy_addr; if (macb_is_gem(macb)) sprintf(netdev->name, "gmac%d", id); else sprintf(netdev->name, "macb%d", id); netdev->init = macb_init; netdev->halt = macb_halt; netdev->send = macb_send; netdev->recv = macb_recv; netdev->write_hwaddr = macb_write_hwaddr; /* * Do some basic initialization so that we at least can talk * to the PHY */ if (macb_is_gem(macb)) { ncfgr = gem_mdc_clk_div(id, macb); ncfgr |= GEM_BF(DBW, 1); } else { ncfgr = macb_mdc_clk_div(id, macb); } macb_writel(macb, NCFGR, ncfgr); eth_register(netdev); #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); macb->bus = miiphy_get_dev_by_name(netdev->name); #endif return 0; }
int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, int phy_addr, u32 emio) { struct eth_device *dev; struct zynq_gem_priv *priv; void *bd_space; dev = calloc(1, sizeof(*dev)); if (dev == NULL) return -1; dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); if (dev->priv == NULL) { free(dev); return -1; } priv = dev->priv; /* Align rxbuffers to ARCH_DMA_MINALIGN */ priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); /* Align bd_space to MMU_SECTION_SHIFT */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, DCACHE_OFF); /* Initialize the bd spaces for tx and rx bd's */ priv->tx_bd = (struct emac_bd *)bd_space; priv->rx_bd = (struct emac_bd *)((unsigned long)bd_space + BD_SEPRN_SPACE); priv->phyaddr = phy_addr; priv->emio = emio; #ifndef CONFIG_ZYNQ_GEM_INTERFACE priv->interface = PHY_INTERFACE_MODE_MII; #else priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; #endif sprintf(dev->name, "Gem.%lx", base_addr); dev->iobase = base_addr; dev->init = zynq_gem_init; dev->halt = zynq_gem_halt; dev->send = zynq_gem_send; dev->recv = zynq_gem_recv; dev->write_hwaddr = zynq_gem_setup_mac; eth_register(dev); miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); priv->bus = miiphy_get_dev_by_name(dev->name); return 1; }
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) { struct macb_device *macb; struct eth_device *netdev; unsigned long macb_hz; u32 ncfgr; macb = malloc(sizeof(struct macb_device)); if (!macb) { printf("Error: Failed to allocate memory for MACB%d\n", id); return -1; } memset(macb, 0, sizeof(struct macb_device)); netdev = &macb->netdev; macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE, &macb->rx_buffer_dma); macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc), &macb->rx_ring_dma); macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc), &macb->tx_ring_dma); macb->regs = regs; macb->phy_addr = phy_addr; sprintf(netdev->name, "macb%d", id); netdev->init = macb_init; netdev->halt = macb_halt; netdev->send = macb_send; netdev->recv = macb_recv; netdev->write_hwaddr = macb_write_hwaddr; /* * Do some basic initialization so that we at least can talk * to the PHY */ macb_hz = get_macb_pclk_rate(id); if (macb_hz < 20000000) ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); else if (macb_hz < 40000000) ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); else if (macb_hz < 80000000) ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); else ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); macb_writel(macb, NCFGR, ncfgr); eth_register(netdev); #if defined(CONFIG_CMD_MII) miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); #endif return 0; }
int uec_initialize(bd_t *bis, uec_info_t *uec_info) { struct eth_device *dev; int i; uec_private_t *uec; int err; dev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!dev) return 0; memset(dev, 0, sizeof(struct eth_device)); /* Allocate the UEC private struct */ uec = (uec_private_t *)malloc(sizeof(uec_private_t)); if (!uec) { return -ENOMEM; } memset(uec, 0, sizeof(uec_private_t)); /* Adjust uec_info */ #if (MAX_QE_RISC == 4) uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS; uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS; #endif devlist[uec_info->uf_info.ucc_num] = dev; uec->uec_info = uec_info; uec->dev = dev; sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num); dev->iobase = 0; dev->priv = (void *)uec; dev->init = uec_init; dev->halt = uec_halt; dev->send = uec_send; dev->recv = uec_recv; /* Clear the ethnet address */ for (i = 0; i < 6; i++) dev->enetaddr[i] = 0; eth_register(dev); err = uec_startup(uec); if (err) { printf("%s: Cannot configure net device, aborting.",dev->name); return err; } #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write); #endif return 1; }
int sh_eth_initialize(bd_t *bd) { int ret = 0; struct sh_eth_dev *eth = NULL; struct eth_device *dev = NULL; eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); if (!eth) { printf(SHETHER_NAME ": %s: malloc failed\n", __func__); ret = -ENOMEM; goto err; } dev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!dev) { printf(SHETHER_NAME ": %s: malloc failed\n", __func__); ret = -ENOMEM; goto err; } memset(dev, 0, sizeof(struct eth_device)); memset(eth, 0, sizeof(struct sh_eth_dev)); eth->port = CONFIG_SH_ETHER_USE_PORT; eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; dev->priv = (void *)eth; dev->iobase = 0; dev->init = sh_eth_init; dev->halt = sh_eth_halt; dev->send = sh_eth_send; dev->recv = sh_eth_recv; eth->port_info[eth->port].dev = dev; sprintf(dev->name, SHETHER_NAME); /* Register Device to EtherNet subsystem */ eth_register(dev); bb_miiphy_buses[0].priv = eth; miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) puts("Please set MAC address\n"); return ret; err: if (dev) free(dev); if (eth) free(eth); printf(SHETHER_NAME ": Failed\n"); return ret; }
int stmmac_mdiobus_driver_init(void) { stmmac_mdio_local_device.iobase_phys = STMMAC_MDIO_IO_BASE; stmmac_mdio_local_device.iobase = STMMAC_MDIO_IO_BASE; stmmac_mdio_clk_init(&stmmac_mdio_local_device); /* GMAC0 PHY init */ miiphy_register(GMAC0_PHY_NAME, stmmac_mdiobus_read, stmmac_mdiobus_write); if (!get_phy_device(GMAC0_PHY_NAME, GMAC0_PHY_ADDR)) miiphy_set_current_dev(GMAC0_PHY_NAME); return 0; }
/* * setup Gbit PHYs */ int last_stage_init(void) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); unsigned int k; miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, bb_miiphy_read, bb_miiphy_write); for (k = 0; k < 32; ++k) configure_gbit_phy(k); /* take fpga serdes blocks out of reset */ out_le16(&fpga->quad_serdes_reset, 0); return 0; }
/* * setup Gbit PHYs */ int last_stage_init(void) { unsigned int k; print_fpga_info(); miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, bb_miiphy_read, bb_miiphy_write); for (k = 0; k < 32; ++k) configure_gbit_phy(k); /* take fpga serdes blocks out of reset */ FPGA_SET_REG(0, quad_serdes_reset, 0); return 0; }
int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, unsigned long dma_addr) { struct eth_device *dev; struct axidma_priv *priv; dev = calloc(1, sizeof(struct eth_device)); if (dev == NULL) return -1; dev->priv = calloc(1, sizeof(struct axidma_priv)); if (dev->priv == NULL) { free(dev); return -1; } priv = dev->priv; sprintf(dev->name, "aximac.%lx", base_addr); dev->iobase = base_addr; priv->dmatx = (struct axidma_reg *)dma_addr; /* RX channel offset is 0x30 */ priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30); dev->init = axiemac_init; dev->halt = axiemac_halt; dev->send = axiemac_send; dev->recv = axiemac_recv; dev->write_hwaddr = axiemac_setup_mac; #ifdef CONFIG_PHY_ADDR priv->phyaddr = CONFIG_PHY_ADDR; #else priv->phyaddr = -1; #endif eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write); priv->bus = miiphy_get_dev_by_name(dev->name); priv->bus->reset = axiemac_bus_reset; #endif return 1; }
int at91emac_register(bd_t *bis, unsigned long iobase) { emac_device *emac; emac_device *emacfix; struct eth_device *dev; if (iobase == 0) iobase = AT91_EMAC_BASE; emac = malloc(sizeof(*emac)+512); if (emac == NULL) return 1; dev = malloc(sizeof(*dev)); if (dev == NULL) { free(emac); return 1; } /* alignment as per Errata (64 bytes) is insufficient! */ emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); memset(emacfix, 0, sizeof(emac_device)); memset(dev, 0, sizeof(*dev)); #ifndef CONFIG_RMII sprintf(dev->name, "AT91 EMAC"); #else sprintf(dev->name, "AT91 EMAC RMII"); #endif dev->iobase = iobase; dev->priv = emacfix; dev->init = at91emac_init; dev->halt = at91emac_halt; dev->send = at91emac_send; dev->recv = at91emac_recv; dev->write_hwaddr = at91emac_write_hwaddr; eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write); #endif return 1; }
int au1x00_enet_initialize(bd_t *bis){ struct eth_device* dev; dev = (struct eth_device*) malloc(sizeof *dev); memset(dev, 0, sizeof *dev); sprintf(dev->name, "Au1X00 ETHERNET"); dev->iobase = 0; dev->priv = 0; dev->init = au1x00_init; dev->halt = au1x00_halt; dev->send = au1x00_send; dev->recv = au1x00_recv; eth_register(dev); #if (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register(dev->name, au1x00_miiphy_read, au1x00_miiphy_write); #endif return 1; }
int bcm_sf2_eth_register(bd_t *bis, u8 dev_num) { struct eth_device *dev; struct eth_info *eth; int rc; dev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (dev == NULL) { error("%s: Not enough memory!\n", __func__); return -1; } eth = (struct eth_info *)malloc(sizeof(struct eth_info)); if (eth == NULL) { error("%s: Not enough memory!\n", __func__); return -1; } printf(banner); memset(dev, 0, sizeof(*dev)); sprintf(dev->name, "%s_%s-%hu", BCM_SF2_ETH_DEV_NAME, BCM_SF2_ETH_MAC_NAME, dev_num); dev->priv = (void *)eth; dev->iobase = 0; dev->init = bcm_sf2_eth_open; dev->halt = bcm_sf2_eth_close; dev->send = bcm_sf2_eth_send; dev->recv = bcm_sf2_eth_receive; dev->write_hwaddr = bcm_sf2_eth_write_hwaddr; #ifdef CONFIG_BCM_SF2_ETH_GMAC if (gmac_add(dev)) { free(eth); free(dev); error("%s: Adding GMAC failed!\n", __func__); return -1; } #else #error "bcm_sf2_eth: NEED to register a MAC!" #endif eth_register(dev); #ifdef CONFIG_CMD_MII miiphy_register(dev->name, eth->miiphy_read, eth->miiphy_write); #endif /* Initialization */ debug("Ethernet initialization ..."); rc = bcm_sf2_eth_init(dev); if (rc != 0) { error("%s: configuration failed!\n", __func__); return -1; } printf("Basic ethernet functionality initialized\n"); return 0; }
/* enter all the galileo ethernet devs into MULTI-BOOT */ void gt6426x_eth_initialize(bd_t *bis) { struct eth_device *dev; struct eth_dev_s *p; int devnum, x, temp; char *s, *e, buf[64]; #ifdef DEBUG printf( "\n%s\n", __FUNCTION ); #endif for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) { dev = calloc(sizeof(*dev), 1); if (!dev) { printf( "%s: gal_enet%d allocation failure, %s\n", __FUNCTION__, devnum, "eth_device structure"); return; } /* must be less than sizeof(dev->name) */ sprintf(dev->name, "gal_enet%d", devnum); #ifdef DEBUG printf( "Initializing %s\n", dev->name ); #endif /* Extract the MAC address from the environment */ switch (devnum) { case 0: s = "ethaddr"; break; #if (GAL_ETH_DEVS > 1) case 1: s = "eth1addr"; break; #endif #if (GAL_ETH_DEVS > 2) case 2: s = "eth2addr"; break; #endif default: /* this should never happen */ printf( "%s: Invalid device number %d\n", __FUNCTION__, devnum ); return; } temp = getenv_f(s, buf, sizeof(buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG printf ("Setting MAC %d to %s\n", devnum, s ); #endif for (x = 0; x < 6; ++x) { dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0; if (s) s = (*e) ? e+1 : e; } dev->init = (void*)gt6426x_eth_probe; dev->halt = (void*)gt6426x_eth_reset; dev->send = (void*)gt6426x_eth_transmit; dev->recv = (void*)gt6426x_eth_poll; p = calloc( sizeof(*p), 1 ); dev->priv = (void*)p; if (!p) { printf( "%s: %s allocation failure, %s\n", __FUNCTION__, dev->name, "Private Device Structure"); free(dev); return; } p->dev = devnum; p->tdn=0; p->rdn=0; p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS; p->eth_tx_desc = (eth0_tx_desc_single *) (((unsigned int) malloc(sizeof (eth0_tx_desc_single) * (NT+1)) & 0xfffffff0) + 0x10); if (!p) { printf( "%s: %s allocation failure, %s\n", __FUNCTION__, dev->name, "Tx Descriptor"); free(dev); return; } p->eth_rx_desc = (eth0_rx_desc_single *) (((unsigned int) malloc(sizeof (eth0_rx_desc_single) * (NR+1)) & 0xfffffff0) + 0x10); if (!p->eth_rx_desc) { printf( "%s: %s allocation failure, %s\n", __FUNCTION__, dev->name, "Rx Descriptor"); free(dev); free(p); return; } p->eth_tx_buffer = (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); if (!p->eth_tx_buffer) { printf( "%s: %s allocation failure, %s\n", __FUNCTION__, dev->name, "Tx Bufffer"); free(dev); free(p); free(p->eth_rx_desc); return; } for (temp = 0 ; temp < NR ; temp ++) { p->eth_rx_buffer[temp] = (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10); if (!p->eth_rx_buffer[temp]) { printf( "%s: %s allocation failure, %s\n", __FUNCTION__, dev->name, "Rx Buffers"); free(dev); free(p); free(p->eth_tx_buffer); free(p->eth_rx_desc); free(p->eth_tx_desc); while (temp >= 0) free(p->eth_rx_buffer[--temp]); return; } } eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, gt6426x_miiphy_read, gt6426x_miiphy_write); #endif } }
int ag7240_enet_initialize(bd_t * bis) { struct eth_device *dev[CFG_AG7240_NMACS]; u32 mask, mac_h, mac_l; int i; #ifdef AG7240_DEBUG printf("ag7240_enet_initialize...\n"); #endif // TODO check this register! ar7240_reg_wr(HORNET_BOOTSTRAP_STATUS, ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & ~HORNET_BOOTSTRAP_MDIO_SLAVE_MASK); if (is_ar933x()) { u32 rd = 0x0; /* * To get s26 out of reset, we have to... * bit0~bit3: has to be deasserted * bit4: has to be asserted */ rd = ar7240_reg_rd(AR7240_S26_CLK_CTRL_OFFSET) & ~(0x1f); rd |= 0x10; ar7240_reg_wr(AR7240_S26_CLK_CTRL_OFFSET, rd); if (ar7240_reg_rd(AR7240_RESET) != 0) { ar7240_reg_wr(AR7240_RESET, 0); } } for (i = 0; i < CFG_AG7240_NMACS; i++) { if ((dev[i] = (struct eth_device *) malloc(sizeof(struct eth_device))) == NULL) { puts("## Error: malloc failed\n"); return 0; } if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof(ag7240_mac_t))) == NULL) { puts("## Error: malloc failed\n"); return 0; } memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i])); memset(dev[i], 0, sizeof(dev[i])); sprintf(dev[i]->name, "eth%d", i); ag7240_get_ethaddr(dev[i]); ag7240_macs[i]->mac_unit = i; ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE; ag7240_macs[i]->dev = dev[i]; dev[i]->iobase = 0; dev[i]->init = ag7240_clean_rx; dev[i]->halt = ag7240_halt; dev[i]->send = ag7240_send; dev[i]->recv = ag7240_recv; dev[i]->priv = (void *) ag7240_macs[i]; } for (i = 0; i < CFG_AG7240_NMACS; i++) { eth_register(dev[i]); #if(CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write); #endif ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST); if (!i) { mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY); if (is_ar7241() || is_ar7242() || is_wasp()){ mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO; } ar7240_reg_rmw_set(AR7240_RESET, mask); if (!is_ar933x()){ udelay(1000 * 100); } ar7240_reg_rmw_clear(AR7240_RESET, mask); if (!is_ar933x()){ udelay(1000 * 100); } if (!is_ar933x()){ udelay(10 * 1000); } } ag7240_hw_start(ag7240_macs[i]); ag7240_setup_fifos(ag7240_macs[i]); if (!is_ar933x()){ udelay(100 * 1000); } #ifdef AG7240_DEBUG unsigned char *mac = dev[i]->enetaddr; printf("\nInterface %s MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff); #endif mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]); mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0); ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l); ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h); /* if using header for register configuration, we have to */ /* configure s26 register after frame transmission is enabled */ if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */ #ifdef CONFIG_AR7242_S16_PHY if (is_ar7242() || is_wasp()) { athrs16_reg_init(); } else #endif { #ifdef CFG_ATHRS26_PHY #ifdef AG7240_DEBUG printf("s26 reg init \n"); #endif athrs26_reg_init(); #endif #ifdef CFG_ATHRS27_PHY #ifdef AG7240_DEBUG printf("s27 reg init \n"); #endif athrs27_reg_init(); #endif #ifdef CONFIG_F1E_PHY #ifdef AG7240_DEBUG printf("F1Phy reg init \n"); #endif athr_reg_init(); #endif } } else { #ifdef CFG_ATHRS26_PHY #ifdef AG7240_DEBUG printf("athrs26_reg_init_lan\n"); #endif athrs26_reg_init_lan(); #endif #ifdef CFG_ATHRS27_PHY #ifdef AG7240_DEBUG printf("s27 reg init lan \n"); #endif athrs27_reg_init_lan(); #endif } #ifdef AG7240_DEBUG printf("ag7240_phy_setup\n"); #endif //udelay(100*1000); ag7240_phy_setup(ag7240_macs[i]->mac_unit); #ifdef AG7240_DEBUG printf("Interface %s is up\n", dev[i]->name); #endif } return 1; }
int kirkwood_egiga_initialize(bd_t * bis) { struct kwgbe_device *dkwgbe; struct eth_device *dev; int devnum; char *s; u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS; for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) { /*skip if port is configured not to use */ if (used_ports[devnum] == 0) continue; if (!(dkwgbe = malloc(sizeof(struct kwgbe_device)))) goto error1; memset(dkwgbe, 0, sizeof(struct kwgbe_device)); if (!(dkwgbe->p_rxdesc = (struct kwgbe_rxdesc *)memalign(PKTALIGN, KW_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1))) goto error2; if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1))) goto error3; if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN))) goto error4; if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *) memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) { free(dkwgbe->p_aligned_txbuf); error4: free(dkwgbe->p_rxbuf); error3: free(dkwgbe->p_rxdesc); error2: free(dkwgbe); error1: printf("Err.. %s Failed to allocate memory\n", __FUNCTION__); return -1; } dev = &dkwgbe->dev; /* must be less than NAMESIZE (16) */ sprintf(dev->name, "egiga%d", devnum); /* Extract the MAC address from the environment */ switch (devnum) { case 0: dkwgbe->regs = (void *)KW_EGIGA0_BASE; s = "ethaddr"; break; case 1: dkwgbe->regs = (void *)KW_EGIGA1_BASE; s = "eth1addr"; break; default: /* this should never happen */ printf("Err..(%s) Invalid device number %d\n", __FUNCTION__, devnum); return -1; } while (!eth_getenv_enetaddr(s, dev->enetaddr)) { /* Generate Random Private MAC addr if not set */ dev->enetaddr[0] = 0x02; dev->enetaddr[1] = 0x50; dev->enetaddr[2] = 0x43; dev->enetaddr[3] = get_random_hex(); dev->enetaddr[4] = get_random_hex(); dev->enetaddr[5] = get_random_hex(); eth_setenv_enetaddr(s, dev->enetaddr); } dev->init = (void *)kwgbe_init; dev->halt = (void *)kwgbe_halt; dev->send = (void *)kwgbe_send; dev->recv = (void *)kwgbe_recv; eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, smi_reg_read, smi_reg_write); /* Set phy address of the port */ miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST, KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); #endif } return 0; }
/* * This function initializes the emac hardware. It does NOT initialize * EMAC modules power or pin multiplexors, that is done by board_init() * much earlier in bootup process. Returns 1 on success, 0 otherwise. */ int davinci_emac_initialize(void) { u_int32_t phy_id; u_int16_t tmp; int i; struct eth_device *dev; dev = malloc(sizeof *dev); if (dev == NULL) return -1; memset(dev, 0, sizeof *dev); sprintf(dev->name, "DaVinci-EMAC"); dev->iobase = 0; dev->init = davinci_eth_open; dev->halt = davinci_eth_close; dev->send = davinci_eth_send_packet; dev->recv = davinci_eth_rcv_packet; dev->write_hwaddr = davinci_eth_set_mac_addr; eth_register(dev); davinci_eth_mdio_enable(); for (i = 0; i < 256; i++) { if (readl(&adap_mdio->ALIVE)) break; udelay(10); } if (i >= 256) { printf("No ETH PHY detected!!!\n"); return(0); } /* Find if a PHY is connected and get it's address */ if (!davinci_eth_phy_detect()) return(0); /* Get PHY ID and initialize phy_ops for a detected PHY */ if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { active_phy_addr = 0xff; return(0); } phy_id = (tmp << 16) & 0xffff0000; if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { active_phy_addr = 0xff; return(0); } phy_id |= tmp & 0x0000ffff; switch (phy_id) { case PHY_LXT972: sprintf(phy.name, "LXT972 @ 0x%02x", active_phy_addr); phy.init = lxt972_init_phy; phy.is_phy_connected = lxt972_is_phy_connected; phy.get_link_speed = lxt972_get_link_speed; phy.auto_negotiate = lxt972_auto_negotiate; break; case PHY_DP83848: sprintf(phy.name, "DP83848 @ 0x%02x", active_phy_addr); phy.init = dp83848_init_phy; phy.is_phy_connected = dp83848_is_phy_connected; phy.get_link_speed = dp83848_get_link_speed; phy.auto_negotiate = dp83848_auto_negotiate; break; case PHY_ET1011C: sprintf(phy.name, "ET1011C @ 0x%02x", active_phy_addr); phy.init = gen_init_phy; phy.is_phy_connected = gen_is_phy_connected; phy.get_link_speed = et1011c_get_link_speed; phy.auto_negotiate = gen_auto_negotiate; break; default: sprintf(phy.name, "GENERIC @ 0x%02x", active_phy_addr); phy.init = gen_init_phy; phy.is_phy_connected = gen_is_phy_connected; phy.get_link_speed = gen_get_link_speed; phy.auto_negotiate = gen_auto_negotiate; } printf("Ethernet PHY: %s\n", phy.name); miiphy_register(phy.name, davinci_mii_phy_read, davinci_mii_phy_write); return(1); }
int last_stage_init(void) { int slaves; unsigned int k; unsigned int mux_ch; unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; bool hw_type_cat = pca9698_get_value(0x20, 18); bool ch0_sgmii2_present = false; /* Turn on Analog Devices ADV7611 */ pca9698_direction_output(0x20, 8, 0); /* Turn on Parade DP501 */ pca9698_direction_output(0x20, 9, 1); ch0_sgmii2_present = !pca9698_get_value(0x20, 37); /* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { unsigned int ctr = 0; if (i2c_probe(mclink_controllers[k])) continue; while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { udelay(100000); if (ctr++ > 5) { printf("no done for mclink_controller %d\n", k); break; } } pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0); pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0); udelay(10); pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, MCFPGA_RESET_N); } if (hw_type_cat) { miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, bb_miiphy_write); for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { if ((mux_ch == 1) && !ch0_sgmii2_present) continue; setup_88e1514(bb_miiphy_buses[0].name, mux_ch); } } /* give slave-PLLs and Parade DP501 some time to be up and running */ udelay(500000); mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); mclink_fpgacount = 0; ioep_fpga_print_info(0); if (!adv7611_probe(0)) printf(" Advantiv ADV7611 HDMI Receiver\n"); #ifdef CONFIG_STRIDER_CON if (ioep_fpga_has_osd(0)) osd_probe(0); #endif #ifdef CONFIG_STRIDER_CPU ch7301_probe(0, false); #endif if (slaves <= 0) return 0; mclink_fpgacount = slaves; for (k = 1; k <= slaves; ++k) { ioep_fpga_print_info(k); #ifdef CONFIG_STRIDER_CON if (ioep_fpga_has_osd(k)) osd_probe(k); #endif #ifdef CONFIG_STRIDER_CPU FPGA_SET_REG(k, extended_control, 0); /* enable video in*/ if (!adv7611_probe(k)) printf(" Advantiv ADV7611 HDMI Receiver\n"); ch7301_probe(k, false); #endif if (hw_type_cat) { miiphy_register(bb_miiphy_buses[k].name, bb_miiphy_read, bb_miiphy_write); setup_88e1514(bb_miiphy_buses[k].name, 0); } } for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) { i2c_set_bus_num(strider_fans[k].bus); init_fan_controller(strider_fans[k].addr); } return 0; }
static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) { struct eth_device *edev; struct fec_priv *fec; unsigned char ethaddr[6]; uint32_t start; int ret = 0; /* create and fill edev struct */ edev = (struct eth_device *)malloc(sizeof(struct eth_device)); if (!edev) { puts("fec_mxc: not enough malloc memory for eth_device\n"); ret = -ENOMEM; goto err1; } fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); if (!fec) { puts("fec_mxc: not enough malloc memory for fec_priv\n"); ret = -ENOMEM; goto err2; } memset(edev, 0, sizeof(*edev)); memset(fec, 0, sizeof(*fec)); edev->priv = fec; edev->init = fec_init; edev->send = fec_send; edev->recv = fec_recv; edev->halt = fec_halt; edev->write_hwaddr = fec_set_hwaddr; fec->eth = (struct ethernet_regs *)base_addr; fec->bd = bd; fec->xcv_type = CONFIG_FEC_XCV_TYPE; /* Reset chip. */ writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); start = get_timer(0); while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { printf("FEC MXC: Timeout reseting chip\n"); goto err3; } udelay(10); } /* * Set interrupt mask register */ writel(0x00000000, &fec->eth->imask); /* * Clear FEC-Lite interrupt event register(IEVENT) */ writel(0xffffffff, &fec->eth->ievent); /* * Set FEC-Lite receive control register(R_CNTRL): */ /* * Frame length=1518; MII mode; */ writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl); fec_mii_setspeed(fec); if (dev_id == -1) { sprintf(edev->name, "FEC"); fec->dev_id = 0; } else { sprintf(edev->name, "FEC%i", dev_id); fec->dev_id = dev_id; } fec->phy_id = phy_id; miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); eth_register(edev); if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); memcpy(edev->enetaddr, ethaddr, 6); } return ret; err3: free(fec); err2: free(edev); err1: return ret; }
int ftmac110_initialize(bd_t *bis) { int i, card_nr = 0; struct eth_device *dev; struct ftmac110_chip *chip; dev = malloc(sizeof(*dev) + sizeof(*chip)); if (dev == NULL) { panic("ftmac110: out of memory 1\n"); return -1; } chip = (struct ftmac110_chip *)(dev + 1); memset(dev, 0, sizeof(*dev) + sizeof(*chip)); sprintf(dev->name, "FTMAC110#%d", card_nr); dev->iobase = CONFIG_FTMAC110_BASE; chip->regs = (void __iomem *)dev->iobase; dev->priv = chip; dev->init = ftmac110_probe; dev->halt = ftmac110_halt; dev->send = ftmac110_send; dev->recv = ftmac110_recv; if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr)) eth_random_enetaddr(dev->enetaddr); /* allocate tx descriptors (it must be 16 bytes aligned) */ chip->txd = dma_alloc_coherent( sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma); if (!chip->txd) panic("ftmac110: out of memory 3\n"); memset(chip->txd, 0, sizeof(struct ftmac110_desc) * CFG_TXDES_NUM); for (i = 0; i < CFG_TXDES_NUM; ++i) { void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE); if (!va) panic("ftmac110: out of memory 4\n"); chip->txd[i].vbuf = va; chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va)); chip->txd[i].ctrl = 0; /* owned by SW */ } chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END); chip->txd_idx = 0; /* allocate rx descriptors (it must be 16 bytes aligned) */ chip->rxd = dma_alloc_coherent( sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma); if (!chip->rxd) panic("ftmac110: out of memory 4\n"); memset((void *)chip->rxd, 0, sizeof(struct ftmac110_desc) * CFG_RXDES_NUM); for (i = 0; i < CFG_RXDES_NUM; ++i) { void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2); if (!va) panic("ftmac110: out of memory 5\n"); /* it needs to be exactly 2 bytes aligned */ va = ((uint8_t *)va + 2); chip->rxd[i].vbuf = va; chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va)); chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER | FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE)); } chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END); chip->rxd_idx = 0; eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, ftmac110_mdio_read, ftmac110_mdio_write); #endif card_nr++; return card_nr; }
static void ag7240_get_ethaddr(struct eth_device *dev) { unsigned char *eeprom; unsigned char *mac = dev->enetaddr; #ifndef CONFIG_AR7240_EMU #ifdef CONFIG_ATH_NAND_BR unsigned char sectorBuff[ATH_ETH_MAC_READ_SIZE]; eeprom = ath_eth_mac_addr(sectorBuff); if(eeprom == NULL) { /* mac address will be set to default mac address */ mac[0] = 0xff; } else { #else /* CONFIG_ATH_NAND_BR */ eeprom = ag7240_mac_addr_loc(); #endif /* CONFIG_ATH_NAND_BR */ if (strcmp(dev->name, "eth0") == 0) { memcpy(mac, eeprom, 6); } else if (strcmp(dev->name, "eth1") == 0) { eeprom += 6; memcpy(mac, eeprom, 6); } else { printf("%s: unknown ethernet device %s\n", __func__, dev->name); return; } #ifdef CONFIG_ATH_NAND_BR } #endif /* CONFIG_ATH_NAND_BR */ /* Use fixed address if the above address is invalid */ if (mac[0] != 0x00 || (mac[0] == 0xff && mac[5] == 0xff)) { #else if (1) { #endif mac[0] = 0x00; mac[1] = 0x03; mac[2] = 0x7f; mac[3] = 0x09; mac[4] = 0x0b; mac[5] = 0xad; printf("No valid address in Flash. Using fixed address\n"); } else { printf("Fetching MAC Address from 0x%p\n", __func__, eeprom); } } int ag7240_enet_initialize(bd_t * bis) { struct eth_device *dev[CFG_AG7240_NMACS]; u32 mask, mac_h, mac_l; int i; printf("ag934x_enet_initialize...\n"); if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0)) ar7240_reg_wr(AR7240_RESET,0); if(is_ar933x()) //Turn on LED ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28) | (0xF8)); for (i = 0; i < CFG_AG7240_NMACS; i++) { if ((dev[i] = (struct eth_device *) malloc(sizeof (struct eth_device))) == NULL) { puts("malloc failed\n"); return 0; } if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof (ag7240_mac_t))) == NULL) { puts("malloc failed\n"); return 0; } memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i])); memset(dev[i], 0, sizeof(dev[i])); sprintf(dev[i]->name, "eth%d", i); ag7240_get_ethaddr(dev[i]); ag7240_macs[i]->mac_unit = i; ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ; ag7240_macs[i]->dev = dev[i]; dev[i]->iobase = 0; dev[i]->init = ag7240_clean_rx; dev[i]->halt = ag7240_halt; dev[i]->send = ag7240_send; dev[i]->recv = ag7240_recv; dev[i]->priv = (void *)ag7240_macs[i]; } #if !defined(CONFIG_ATH_NAND_BR) mask = AR7240_RESET_GE1_PHY; ar7240_reg_rmw_set(AR7240_RESET, mask); udelay(1000 * 100); ar7240_reg_rmw_clear(AR7240_RESET, mask); udelay(100); #endif mask = AR7240_RESET_GE0_PHY; ar7240_reg_rmw_set(AR7240_RESET, mask); udelay(1000 * 100); ar7240_reg_rmw_clear(AR7240_RESET, mask); udelay(100); for (i = 0; i < CFG_AG7240_NMACS; i++) { eth_register(dev[i]); #if(CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write); #endif ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST); if(!i) { mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE1_MAC); if (is_ar7241() || is_ar7242() || is_wasp()) mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO; printf(" wasp reset mask:%x \n",mask); ar7240_reg_rmw_set(AR7240_RESET, mask); udelay(1000 * 100); ar7240_reg_rmw_clear(AR7240_RESET, mask); udelay(1000 * 100); udelay(10 * 1000); } ag7240_mii_setup(ag7240_macs[i]); /* if using header for register configuration, we have to */ /* configure s26 register after frame transmission is enabled */ if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */ #ifdef CONFIG_AR7242_S16_PHY if (is_ar7242() || is_wasp()) { athrs16_reg_init(); } else #endif { #ifdef CONFIG_ATHRS17_PHY athrs17_reg_init(); #endif #ifdef CFG_ATHRS26_PHY athrs26_reg_init(); #endif #ifdef CFG_ATHRS27_PHY printf("s27 reg init \n"); athrs27_reg_init(); #endif #ifdef CONFIG_F1E_PHY printf("F1Phy reg init \n"); athr_reg_init(); #endif #ifdef CONFIG_VIR_PHY printf("VIRPhy reg init \n"); athr_vir_reg_init(); #endif #ifdef CONFIG_F2E_PHY printf("F2Phy reg init \n"); athr_reg_init(); #endif } } else { #ifdef CFG_ATHRS26_PHY athrs26_reg_init_lan(); #endif #ifdef CFG_ATHRS27_PHY printf("s27 reg init lan \n"); athrs27_reg_init_lan(); #endif } ag7240_hw_start(ag7240_macs[i]); ag7240_setup_fifos(ag7240_macs[i]); udelay(100 * 1000); { unsigned char *mac = dev[i]->enetaddr; printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff); } mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]); mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0); ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l); ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h); ag7240_phy_setup(ag7240_macs[i]->mac_unit); printf("%s up\n",dev[i]->name); } return 1; } #if (CONFIG_COMMANDS & CFG_CMD_MII) int ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t *data) { ag7240_mac_t *mac = ag7240_name2mac(devname); uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg, val; volatile int rddata; uint16_t ii = 0xFFFF; /* * Check for previous transactions are complete. Added to avoid * race condition while running at higher frequencies. */ do { udelay(5); rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1; } while(rddata && --ii); if (ii == 0) printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__); ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0); ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr); ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, AG7240_MGMT_CMD_READ); do { udelay(5); rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1; } while(rddata && --ii); if(ii==0) printf("Error!!! Leave ag7240_miiphy_read without polling correct status!\n"); val = ag7240_reg_rd(mac, AG7240_MII_MGMT_STATUS); ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0); if(data != NULL) *data = val; return val; }
int ag7240_enet_initialize(bd_t * bis){ struct eth_device *dev[CFG_AG7240_NMACS]; u32 mask, mac_h, mac_l; int i; //printf("ag934x_enet_initialize...\n"); /* if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0)){ ar7240_reg_wr(AR7240_RESET,0); } if(is_ar933x()) //Turn on LED ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28) | (0xF8)); */ for(i = 0;i < CFG_AG7240_NMACS;i++){ if((dev[i] = (struct eth_device *)malloc(sizeof(struct eth_device))) == NULL){ //puts("malloc failed\n"); return(0); } if((ag7240_macs[i] = (ag7240_mac_t *)malloc(sizeof(ag7240_mac_t))) == NULL){ //puts("malloc failed\n"); return(0); } memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i])); memset(dev[i], 0, sizeof(dev[i])); sprintf(dev[i]->name, "eth%d", i); ag7240_get_ethaddr(dev[i]); ag7240_macs[i]->mac_unit = i; ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ; ag7240_macs[i]->dev = dev[i]; dev[i]->iobase = 0; dev[i]->init = ag7240_clean_rx; dev[i]->halt = ag7240_halt; dev[i]->send = ag7240_send; dev[i]->recv = ag7240_recv; dev[i]->priv = (void *)ag7240_macs[i]; } for(i = 0;i < CFG_AG7240_NMACS;i++){ eth_register(dev[i]); #if(CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write); #endif ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST); if(!i){ mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY); if(is_ar7241() || is_ar7242() || is_wasp()){ mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO; } //printf(" wasp reset mask:%x \n",mask); ar7240_reg_rmw_set(AR7240_RESET, mask); udelay(1000 * 100); ar7240_reg_rmw_clear(AR7240_RESET, mask); udelay(1000 * 100); udelay(10 * 1000); } ag7240_hw_start(ag7240_macs[i]); ag7240_setup_fifos(ag7240_macs[i]); udelay(100 * 1000); //unsigned char *mac = dev[i]->enetaddr; //printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff); mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]); mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0); ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l); ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h); /* if using header for register configuration, we have to */ /* configure s26 register after frame transmission is enabled */ if(ag7240_macs[i]->mac_unit == 0){ /* WAN Phy */ #ifdef CONFIG_AR7242_S16_PHY if(is_ar7242() || is_wasp()){ athrs16_reg_init(); } else #endif { #ifdef CFG_ATHRS17_PHY athrs17_reg_init(); #endif #ifdef CFG_ATHRS26_PHY athrs26_reg_init(); #endif #ifdef CFG_ATHRS27_PHY //printf("s27 reg init \n"); athrs27_reg_init(); #endif #ifdef CONFIG_F1E_PHY //printf("F1Phy reg init \n"); athr_reg_init(); #endif #ifdef CONFIG_VIR_PHY //printf("VIRPhy reg init \n"); athr_vir_reg_init(); #endif #ifdef CONFIG_F2E_PHY //printf("F2Phy reg init \n"); athr_reg_init(); #endif } } else { #ifdef CFG_ATHRS26_PHY athrs26_reg_init_lan(); #endif #ifdef CFG_ATHRS27_PHY //printf("s27 reg init lan \n"); athrs27_reg_init_lan(); #endif } ag7240_phy_setup(ag7240_macs[i]->mac_unit); //printf("%s up\n",dev[i]->name); } return(1); }
int dm644x_eth_miiphy_initialize(bd_t *bis) { miiphy_register(phy.name, dm644x_mii_phy_read, dm644x_mii_phy_write); return(1); }
int mvgbe_initialize(bd_t *bis) { struct mvgbe_device *dmvgbe; struct eth_device *dev; int devnum; u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS; for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { /*skip if port is configured not to use */ if (used_ports[devnum] == 0) continue; dmvgbe = malloc(sizeof(struct mvgbe_device)); if (!dmvgbe) goto error1; memset(dmvgbe, 0, sizeof(struct mvgbe_device)); dmvgbe->p_rxdesc = (struct mvgbe_rxdesc *)memalign(PKTALIGN, MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1); if (!dmvgbe->p_rxdesc) goto error2; dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ*PKTSIZE_ALIGN + 1); if (!dmvgbe->p_rxbuf) goto error3; dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); if (!dmvgbe->p_aligned_txbuf) goto error4; dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign( PKTALIGN, sizeof(struct mvgbe_txdesc) + 1); if (!dmvgbe->p_txdesc) { free(dmvgbe->p_aligned_txbuf); error4: free(dmvgbe->p_rxbuf); error3: free(dmvgbe->p_rxdesc); error2: free(dmvgbe); error1: printf("Err.. %s Failed to allocate memory\n", __FUNCTION__); return -1; } dev = &dmvgbe->dev; /* must be less than NAMESIZE (16) */ sprintf(dev->name, "egiga%d", devnum); switch (devnum) { case 0: dmvgbe->regs = (void *)MVGBE0_BASE; break; #if defined(MVGBE1_BASE) case 1: dmvgbe->regs = (void *)MVGBE1_BASE; break; #endif default: /* this should never happen */ printf("Err..(%s) Invalid device number %d\n", __FUNCTION__, devnum); return -1; } dev->init = (void *)mvgbe_init; dev->halt = (void *)mvgbe_halt; dev->send = (void *)mvgbe_send; dev->recv = (void *)mvgbe_recv; dev->write_hwaddr = (void *)mvgbe_write_hwaddr; eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) miiphy_register(dev->name, smi_reg_read, smi_reg_write); /* Set phy address of the port */ miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); #endif } return 0; }
int ep93xx_miiphy_initialize(bd_t * const bd) { miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write); return 0; }
int last_stage_init(void) { unsigned int k; unsigned int fpga; int failed = 0; char str_phys[] = "Setup PHYs -"; char str_serdes[] = "Start SERDES blocks"; char str_channels[] = "Start FPGA channels"; char str_locks[] = "Verify SERDES locks"; char str_hicb[] = "Verify HICB status"; char str_status[] = "Verify PHY status -"; char slash[] = "\\|/-\\|/-"; print_fpga_info(0); print_fpga_info(1); /* setup Gbit PHYs */ puts("TRANS: "); puts(str_phys); miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, bb_miiphy_read, bb_miiphy_write); for (k = 0; k < 32; ++k) { configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k); putc('\b'); putc(slash[k % 8]); } miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME, bb_miiphy_read, bb_miiphy_write); for (k = 0; k < 32; ++k) { configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k); putc('\b'); putc(slash[k % 8]); } blank_string(strlen(str_phys)); /* take fpga serdes blocks out of reset */ puts(str_serdes); udelay(500000); FPGA_SET_REG(0, quad_serdes_reset, 0); FPGA_SET_REG(1, quad_serdes_reset, 0); blank_string(strlen(str_serdes)); /* take channels out of reset */ puts(str_channels); udelay(500000); for (fpga = 0; fpga < 2; ++fpga) { for (k = 0; k < 32; ++k) FPGA_SET_REG(fpga, ch[k].config_int, 0); } blank_string(strlen(str_channels)); /* verify channels serdes lock */ puts(str_locks); udelay(500000); for (fpga = 0; fpga < 2; ++fpga) { for (k = 0; k < 32; ++k) { u16 status; FPGA_GET_REG(k, ch[k].status_int, &status); if (!(status & (1 << 4))) { failed = 1; printf("fpga %d channel %d: no serdes lock\n", fpga, k); } /* reset events */ FPGA_SET_REG(fpga, ch[k].status_int, 0); } } blank_string(strlen(str_locks)); /* verify hicb_status */ puts(str_hicb); for (fpga = 0; fpga < 2; ++fpga) { for (k = 0; k < 32; ++k) { u16 status; FPGA_GET_REG(k, hicb_ch[k].status_int, &status); if (status) printf("fpga %d hicb %d: hicb status %04x\n", fpga, k, status); /* reset events */ FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0); } } blank_string(strlen(str_hicb)); /* verify phy status */ puts(str_status); for (k = 0; k < 32; ++k) { if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) { printf("verify baseboard phy %d failed\n", k); failed = 1; } putc('\b'); putc(slash[k % 8]); } for (k = 0; k < 32; ++k) { if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) { printf("verify extensionboard phy %d failed\n", k); failed = 1; } putc('\b'); putc(slash[k % 8]); } blank_string(strlen(str_status)); printf("Starting 64 channels %s\n", failed ? "failed" : "ok"); return 0; }