예제 #1
0
void reset_phy (void)
{
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
	volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
#endif
	/* reset Giga bit Ethernet port if needed here */

	/* reset the CPM FEC port */
#if (CONFIG_ETHER_INDEX == 2)
	bcsr->bcsr2 &= ~FETH2_RST;
	udelay(2);
	bcsr->bcsr2 |=  FETH2_RST;
	udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
	bcsr->bcsr3 &= ~FETH3_RST;
	udelay(2);
	bcsr->bcsr3 |=  FETH3_RST;
	udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
	/* reset PHY */
	miiphy_reset("FCC1 ETHERNET", 0x0);

	/* change PHY address to 0x02 */
	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);

	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
}
예제 #2
0
void reset_phy(void)
{
	char *name = "GENERIC @ 0x00";

	/* reset the phy */
	miiphy_reset(name, 0x0);
}
예제 #3
0
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
	u16 reg;
	u16 devadr;
	char *name = "egiga0";

	if (miiphy_set_current_dev(name))
		return;

	/* command to read PHY dev address */
	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
		printf("Err..%s could not read PHY dev address\n",
			__FUNCTION__);
		return;
	}

	/*
	 * Enable RGMII delay on Tx and Rx for CPU port
	 * Ref: sec 4.7.2 of chip datasheet
	 */
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);

	/* reset the phy */
	miiphy_reset(name, devadr);

	printf("88E1116 Initialized on %s\n", name);
}
예제 #4
0
파일: common.c 프로젝트: 01hyang/u-boot
void mv_phy_88e1318_init(const char *name, u16 phyaddr)
{
	u16 reg;

	if (miiphy_set_current_dev(name))
		return;

	/*
	 * Set control mode 4 for LED[0].
	 */
	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
	miiphy_read(name, phyaddr, 16, &reg);
	reg |= 0xf;
	miiphy_write(name, phyaddr, 16, reg);

	/*
	 * Enable RGMII delay on Tx and Rx for CPU port
	 * Ref: sec 4.7.2 of chip datasheet
	 */
	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
	miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
	reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
	miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);

	if (miiphy_reset(name, phyaddr) == 0)
		printf("88E1318 Initialized on %s\n", name);
}
예제 #5
0
void reset_phy (void)
{
	u16 id1, id2;

	/* initialize the PHY */
	miiphy_reset ("NPE0", CONFIG_PHY_ADDR);

	miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
	miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);

	id2 &= 0xFFF0;		/* mask out revision bits */

	if (id1 == 0x13 && id2 == 0x78e0) {
		/*
		 * LXT971/LXT972 PHY: set LED outputs:
		 * LED1(green) = Link/ACT,
		 * LED2 (unused) = LINK,
		 * LED3(red) = Coll
		 */
		miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
	} else if (id1 == 0x143 && id2 == 0xbc30) {
		/* BCM5241: default values are OK */
	} else
		printf ("unknown ethernet PHY ID: %x %x\n", id1, id2);
}
예제 #6
0
void reset_phy (void)
{
#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
	volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR;
#endif
	/* reset Giga bit Ethernet port if needed here */

	/* reset the CPM FEC port */
#if (CONFIG_ETHER_INDEX == 2)
	bcsr[0] &= ~0x20;
	udelay(2);
	bcsr[0] |= 0x20;
	udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
	bcsr[0] &= ~0x10;
	udelay(2);
	bcsr[0] |= 0x10;
	udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
	/* reset PHY */
	miiphy_reset("FCC1 ETHERNET", 0x0);

	/* change PHY address to 0x02 */
	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);

	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
}
예제 #7
0
/* Configure and enable MV88E1118 PHY */
void reset_phy(void)
{
	char *name = "egiga0";

	if (miiphy_set_current_dev(name))
		return;

	/* reset the phy */
	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}
예제 #8
0
파일: mii-drv.c 프로젝트: Hi-Spy/hi_u-boot
void hieth_mdiobus_driver_exit(void)
{
    /*add this to avoid the first time to use eth will print 'No such device: XXXXX' message.*/
    if (!miiphy_get_current_dev())
        return;

	/* UpEther PHY exit */
	if(!get_phy_device(U_PHY_NAME,U_PHY_ADDR))
	{
		miiphy_reset(U_PHY_NAME, U_PHY_ADDR);
	}
	
	/* DownEther PHY exit */
	if(!get_phy_device(D_PHY_NAME,D_PHY_ADDR))
	{	
		miiphy_reset(D_PHY_NAME, D_PHY_ADDR);
	}
		
	hieth_mdio_exit(&mdio_bus_ld);
}
예제 #9
0
void
reset_phy(void)
{
	volatile uint *blatch;
#if 0
	int	i;
#endif
	blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;

	/* reset Giga bit Ethernet port if needed here */

#if 1
	*blatch &= ~0x000000c0;
	udelay(100);
#else
	*blatch = 0;
	asm("eieio");
	for (i=0; i<1000; i++)
		udelay(1000);
#endif
	*blatch = 0x000000c1;	/* Light one led, too */
	udelay(1000);

#if 0	/* This is the port we really want to use for debugging. */
	/* reset the CPM FEC port */
#if (CONFIG_ETHER_INDEX == 2)
	bcsr->bcsr2 &= ~FETH2_RST;
	udelay(2);
	bcsr->bcsr2 |=	FETH2_RST;
	udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
	bcsr->bcsr3 &= ~FETH3_RST;
	udelay(2);
	bcsr->bcsr3 |=	FETH3_RST;
	udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
	/* reset PHY */
	miiphy_reset("FCC1 ETHERNET", 0x0);

	/* change PHY address to 0x02 */
	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);

	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_MII */
#endif
}
예제 #10
0
파일: km_arm.c 프로젝트: CogSystems/u-boot
/* Configure and enable MV88E1118 PHY on the piggy*/
void reset_phy(void)
{
	unsigned int oui;
	unsigned char model, rev;

	char *name = "egiga0";

	if (miiphy_set_current_dev(name))
		return;

	/* reset the phy */
	miiphy_reset(name, CONFIG_PHY_BASE_ADR);

	/* get PHY model */
	if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
		return;

	/* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
	if ((oui == PHY_MARVELL_OUI) &&
	    (model == PHY_MARVELL_88E1118R_MODEL)) {
		/* set page register to 3 */
		if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
				 PHY_MARVELL_PAGE_REG,
				 PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
			printf("Error writing PHY page reg\n");

		/*
		 * leds setup as printed on PCB:
		 * LED2 (Link): 0x0 (On Link, Off No Link)
		 * LED1 (Activity): 0x3 (On Activity, Off No Activity)
		 * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
		 */
		if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
				 PHY_MARVELL_88E1118R_LED_CTRL_REG,
				 PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
				 PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
				 PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
				 PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
			printf("Error writing PHY LED reg\n");

		/* set page register back to 0 */
		if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
				 PHY_MARVELL_PAGE_REG,
				 PHY_MARVELL_DEFAULT_PAGE))
			printf("Error writing PHY page reg\n");
	}
}
예제 #11
0
void reset_phy (void)
{
	int i;

	/* initialize the PHY */
	miiphy_reset ("NPE0", CONFIG_PHY_ADDR);

	/* all LED outputs = Link/Act */
	miiphy_write ("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);

	/*
	 * The Marvell 88E6060 switch comes up with all ports disabled.
	 * set all ethernet switch ports to forwarding state
	*/
	for (i = 1; i <= 5; i++)
		miiphy_write ("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);

}
예제 #12
0
/* Configure and enable MV88E3018 PHY */
void reset_phy(void)
{
	char *name = "egiga0";
	unsigned short reg;

	if (miiphy_set_current_dev(name))
		return;

	/* RGMII clk transition on data stable */
	if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, &reg) != 0)
		printf("Error reading PHY spec ctrl reg\n");
	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
		reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
		printf("Error writing PHY spec ctrl reg\n");

	/* leds setup */
	if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
		PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
		printf("Error writing PHY LED reg\n");

	/* reset the phy */
	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
}