static void __init mikasa_init_irq(void) { long i; if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; mikasa_update_irq_hw(0); for (i = 16; i < 32; ++i) { <<<<<<< HEAD irq_set_chip_and_handler(i, &mikasa_irq_type, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); =======
static void __init mikasa_init_irq(void) { long i; if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; mikasa_update_irq_hw(0); for (i = 16; i < 32; ++i) { irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; irq_desc[i].chip = &mikasa_irq_type; } init_i8259a_irqs(); common_init_isa_dma(); }
static void __init mikasa_init_irq(void) { long i; if (alpha_using_srm) alpha_mv.device_interrupt = srm_device_interrupt; mikasa_update_irq_hw(0); for (i = 16; i < 32; ++i) { irq_to_desc(i)->status |= IRQ_LEVEL; set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq); } init_i8259a_irqs(); common_init_isa_dma(); }
static void mikasa_disable_irq(struct irq_data *d) { mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16))); }
static inline void mikasa_enable_irq(struct irq_data *d) { mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16)); }
static void mikasa_disable_irq(unsigned int irq) { mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16))); }
static inline void mikasa_enable_irq(unsigned int irq) { mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16)); }
<<<<<<< HEAD mikasa_enable_irq(struct irq_data *d) { mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16)); }