/**
* Module init.
*
* Register the panel-info.
*
* Some parameters are from the panel datasheet
* and other are *calculated* by the "dsi_timing_program.xlsm"
* excel file
*
* @return int
*/
static int __init mipi_chimei_wuxga_init(void)
{
int ret;
struct msm_panel_info *pinfo = &chimei_wuxga_pinfo;
struct platform_disp_info info = {
.id = DISPLAY_PRIMARY,
.dest = DISPLAY_1
};
if (msm_fb_detect_client("mipi_video_chimei_wuxga", &info))
return 0;
pr_info("mipi-dsi chimei wuxga (1200x1920) driver ver 1.0.\n");
/* Portrait */
pinfo->xres = 1200;
pinfo->yres = 1920;
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->pdest = info.dest;
pinfo->disp_id = info.id;
pinfo->wait_cycle = 0;
pinfo->bpp = 24; /* RGB565 requires 24 bits-per-pixel :-O */
pinfo->fb_num = 2; /* using two frame buffers */
/*
* The CMI panel requires 80 MHZ LVDS-CLK.
* The D2L bridge drives the LVDS-CLK from the DSI-CLK.
* The DSI-CLK = bitclk/2, 640 MHZ/2= 320 MHZ.
* LVDS-CLK = DSI-CLK/4 , 320 MHZ/4= 80 MHZ.
*/
pinfo->clk_rate = 635 * MHZ ; /* bitclk Calculated */
/*
* this panel is operated by DE,
* vsycn and hsync are ignored
*/
pinfo->lcdc.h_front_porch = 160-48-32; /* thfp */
pinfo->lcdc.h_back_porch = 48; /* thb */
pinfo->lcdc.h_pulse_width = 32; /* thpw */
pinfo->lcdc.v_front_porch = 26-3-6; /* tvfp */
pinfo->lcdc.v_back_porch = 3; /* tvb */
pinfo->lcdc.v_pulse_width = 6; /* tvpw */
pinfo->lcdc.border_clr = 0; /* black */
pinfo->lcdc.underflow_clr = 0xff; /* blue */
pinfo->lcdc.hsync_skew = 0;
/* Backlight levels - controled via PMIC pwm gpio */
pinfo->bl_max = PWM_LEVEL;
pinfo->bl_min = 1;
/* mipi - general */
pinfo->mipi.vc = 0; /* virtual channel */
pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
pinfo->mipi.tx_eot_append = true;
pinfo->mipi.t_clk_post = 34; /* Calculated */
pinfo->mipi.t_clk_pre = 69; /* Calculated */
pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db;
/* Four lanes are recomended for 1920x1200 at 60 frames per second */
pinfo->mipi.frame_rate = 60;
pinfo->mipi.data_lane0 = true;
pinfo->mipi.data_lane1 = true;
pinfo->mipi.data_lane2 = true;
pinfo->mipi.data_lane3 = true;
pinfo->mipi.esc_byte_ratio = 6;
pinfo->mipi.mode = DSI_VIDEO_MODE;
/*
* Note: The CMI panel input is RGB888,
* thus the DSI-to-LVDS bridge output is RGB888.
* This parameter selects the DSI-Core output to the bridge.
*/
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB565;
/* mipi - video mode */
pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT;
pinfo->mipi.pulse_mode_hsa_he = false; /* sync mode */
pinfo->mipi.hfp_power_stop = false;
pinfo->mipi.hbp_power_stop = false;
pinfo->mipi.hsa_power_stop = false;
pinfo->mipi.eof_bllp_power_stop = false;
pinfo->mipi.bllp_power_stop = false;
/* mipi - command mode */
pinfo->mipi.te_sel = 1; /* TE from vsycn gpio */
pinfo->mipi.interleave_max = 1;
/* The bridge supports only Generic Read/Write commands */
pinfo->mipi.insert_dcs_cmd = false;
pinfo->mipi.wr_mem_continue = 0;
pinfo->mipi.wr_mem_start = 0;
pinfo->mipi.stream = false; /* dma_p */
pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
/*
* toshiba d2l chip does not need max_pkt_size dcs cmd
* client reply len is directly configure through
* RDPKTLN register (0x0404)
*/
pinfo->mipi.no_max_pkt_size = 1;
pinfo->mipi.force_clk_lane_hs = 1;
pinfo->is_3d_panel = FB_TYPE_3D_PANEL;
ret = mipi_tc358764_dsi2lvds_register(pinfo, MIPI_DSI_PRIM, 1);
if (ret)
pr_err("%s: failed to register device!\n", __func__);
return ret;
}
static int __init mipi_video_samsung_tft_wsvga_pt_init(void)
{
int ret;
if(system_rev) {
printk(KERN_ERR"%s:system_rev:%d..Initialize Quick Logic MIPI2LVDS Converter\n", __func__,system_rev);
return 0;
}
/* Landscape */
pinfo.xres = 1024;
pinfo.yres = 600;
pinfo.mode2_xres = 0;
pinfo.mode2_yres = 0;
pinfo.mode2_bpp = 0;
pinfo.type = MIPI_VIDEO_PANEL;
pinfo.pdest = DISPLAY_1; /* Primary Display */
pinfo.wait_cycle = 0;
pinfo.bpp = 24; /* RGB888 = 24 bits-per-pixel */
pinfo.fb_num = 2; /* using two frame buffers */
/* bitclk */
pinfo.clk_rate = 380000000;
/*
* this panel is operated by DE,
* vsycn and hsync are ignored
*/
pinfo.lcdc.h_front_porch = 25;/* thfp */
pinfo.lcdc.h_back_porch = 25; /* thb */
pinfo.lcdc.h_pulse_width = 470; /* thpw */
pinfo.lcdc.v_front_porch = 58; /* tvfp */
pinfo.lcdc.v_back_porch = 7; /* tvb */
pinfo.lcdc.v_pulse_width = 30; /* tvpw */
pinfo.lcdc.border_clr = 0; /* black */
pinfo.lcdc.underflow_clr = 0xff; /* blue */
pinfo.lcdc.hsync_skew = 0;
/* Backlight levels - controled via PMIC pwm gpio */
pinfo.bl_max = 255;
pinfo.bl_min = 1;
/* mipi - general */
pinfo.mipi.vc = 0; /* virtual channel */
pinfo.mipi.rgb_swap = DSI_RGB_SWAP_RGB;
pinfo.mipi.tx_eot_append = false;//true
pinfo.mipi.t_clk_post = 4; /* Calculated */
pinfo.mipi.t_clk_pre = 16; /* Calculated */
pinfo.mipi.dsi_phy_db = &dsi_video_mode_phy_db;
pinfo.mipi.esc_byte_ratio = 4;
/* Four lanes are recomended for 1366x768 at 60 frames per second */
pinfo.mipi.frame_rate = 60; /* 60 frames per second */
pinfo.mipi.data_lane0 = true;
pinfo.mipi.data_lane1 = true;
pinfo.mipi.data_lane2 = true;
pinfo.mipi.data_lane3 = true;
pinfo.mipi.dlane_swap = 0x00;
pinfo.mipi.mode = DSI_VIDEO_MODE;
/*
* Note: The CMI panel input is RGB888,
* thus the DSI-to-LVDS bridge output is RGB888.
* This parameter selects the DSI-Core output to the bridge.
*/
pinfo.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
/* mipi - video mode */
pinfo.mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT;
pinfo.mipi.pulse_mode_hsa_he = TRUE; /* sync mode */
pinfo.mipi.hfp_power_stop = TRUE;
pinfo.mipi.hbp_power_stop = TRUE;
pinfo.mipi.hsa_power_stop = TRUE;
pinfo.mipi.eof_bllp_power_stop = TRUE;
pinfo.mipi.bllp_power_stop = TRUE;
pinfo.mipi.vc = 0;
/* mipi - command mode */
pinfo.mipi.te_sel = 0;
pinfo.mipi.interleave_max = 1;
/* The bridge supports only Generic Read/Write commands */
pinfo.mipi.insert_dcs_cmd = false;
pinfo.mipi.wr_mem_continue = 0;
pinfo.mipi.wr_mem_start = 0;
pinfo.mipi.stream = false; /* dma_p */
pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW;
pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
/*
* toshiba d2l chip does not need max_pkt_szie dcs cmd
* client reply len is directly configure through
* RDPKTLN register (0x0404)
*/
pinfo.mipi.tx_eot_append = FALSE;
pinfo.mipi.t_clk_post = 0x20;
pinfo.mipi.t_clk_pre = 0x2D;
pinfo.mipi.no_max_pkt_size = 1;
pinfo.mipi.force_clk_lane_hs = 1;
ret = mipi_tc358764_dsi2lvds_register(&pinfo, MIPI_DSI_PRIM,
MIPI_DSI_PANEL_QHD_PT, &dsi2lvds_pd);
if (ret)
pr_err("%s: failed to register device!\n", __func__);
return ret;
}
/**
* Module init.
*
* Register the panel-info.
*
* Some parameters are from the panel datasheet
* and other are *calculated* according to the
* "DSI_panel_bring_up_guide_ver3.docm".
*
* @return int
*/
static int __init mipi_chimei_wxga_init(void)
{
int ret;
struct msm_panel_info *pinfo = &chimei_wxga_pinfo;
if (msm_fb_detect_client("mipi_video_chimei_wxga"))
return 0;
pr_debug("mipi-dsi chimei wxga (1366x768) driver ver 1.0.\n");
/* Landscape */
pinfo->xres = 1366;
pinfo->yres = 768;
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->pdest = DISPLAY_1; /* Primary Display */
pinfo->wait_cycle = 0;
pinfo->bpp = 24; /* RGB888 = 24 bits-per-pixel */
pinfo->fb_num = 2; /* using two frame buffers */
/* bitclk */
pinfo->clk_rate = 473400000; /* 473.4 MHZ Calculated */
/*
* this panel is operated by DE,
* vsycn and hsync are ignored
*/
pinfo->lcdc.h_front_porch = 96+2;/* thfp */
pinfo->lcdc.h_back_porch = 88; /* thb */
pinfo->lcdc.h_pulse_width = 40; /* thpw */
pinfo->lcdc.v_front_porch = 15; /* tvfp */
pinfo->lcdc.v_back_porch = 23; /* tvb */
pinfo->lcdc.v_pulse_width = 20; /* tvpw */
pinfo->lcdc.border_clr = 0; /* black */
pinfo->lcdc.underflow_clr = 0xff; /* blue */
pinfo->lcdc.hsync_skew = 0;
/* Backlight levels - controled via PMIC pwm gpio */
pinfo->bl_max = PWM_LEVEL;
pinfo->bl_min = 1;
/* mipi - general */
pinfo->mipi.vc = 0; /* virtual channel */
pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
pinfo->mipi.tx_eot_append = true;
pinfo->mipi.t_clk_post = 34; /* Calculated */
pinfo->mipi.t_clk_pre = 64; /* Calculated */
pinfo->mipi.esc_byte_ratio = 4;
pinfo->mipi.dsi_phy_db = dsi_video_mode_phy_dbs;
pinfo->mipi.dsi_phy_db_count = ARRAY_SIZE(dsi_video_mode_phy_dbs);
/* Four lanes are recomended for 1366x768 at 60 frames per second */
pinfo->mipi.frame_rate = 60; /* 60 frames per second */
pinfo->mipi.data_lane0 = true;
pinfo->mipi.data_lane1 = true;
pinfo->mipi.data_lane2 = true;
pinfo->mipi.data_lane3 = true;
pinfo->mipi.mode = DSI_VIDEO_MODE;
/*
* Note: The CMI panel input is RGB888,
* thus the DSI-to-LVDS bridge output is RGB888.
* This parameter selects the DSI-Core output to the bridge.
*/
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
/* mipi - video mode */
pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT;
pinfo->mipi.pulse_mode_hsa_he = false; /* sync mode */
pinfo->mipi.hfp_power_stop = false;
pinfo->mipi.hbp_power_stop = false;
pinfo->mipi.hsa_power_stop = false;
pinfo->mipi.eof_bllp_power_stop = false;
pinfo->mipi.bllp_power_stop = false;
/* mipi - command mode */
pinfo->mipi.te_sel = 1; /* TE from vsycn gpio */
pinfo->mipi.interleave_max = 1;
/* The bridge supports only Generic Read/Write commands */
pinfo->mipi.insert_dcs_cmd = false;
pinfo->mipi.wr_mem_continue = 0;
pinfo->mipi.wr_mem_start = 0;
pinfo->mipi.stream = false; /* dma_p */
pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
/*
* toshiba d2l chip does not need max_pkt_szie dcs cmd
* client reply len is directly configure through
* RDPKTLN register (0x0404)
*/
pinfo->mipi.no_max_pkt_size = 1;
pinfo->mipi.force_clk_lane_hs = 1;
ret = mipi_tc358764_dsi2lvds_register(pinfo, MIPI_DSI_PRIM,
MIPI_DSI_PANEL_WXGA);
if (ret)
pr_err("%s: failed to register device!\n", __func__);
return ret;
}
/**
* Module init.
*
* Register the panel-info.
*
* Some parameters are from the panel datasheet
* and other are *calculated* according to the
* "DSI_panel_bring_up_guide_ver3.docm".
*
* @return int
*/
static int __init mipi_boe_wxga_init(void)
{
int ret;
struct msm_panel_info *pinfo = &boe_wxga_pinfo;
pr_debug("mipi-dsi boe wxga (1280x800) driver ver 1.0.\n");
if (msm_fb_detect_client("mipi_boe_wxga"))
return 0;
/* Landscape */
pinfo->xres = 1280;
pinfo->yres = 800;
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->pdest = DISPLAY_1; /* Primary Display */
pinfo->wait_cycle = 0;
pinfo->bpp = 24; /* RGB888 = 24 bits-per-pixel */
pinfo->fb_num = 2; /* using two frame buffers */
/* bitclk */
pinfo->clk_rate = 388785600; /*388.7856 MHZ Calculated */
/*
* this panel is operated by DE,
* vsycn and hsync are ignored
*/
pinfo->lcdc.h_front_porch = 18;/* thfp */
pinfo->lcdc.h_back_porch = 16; /* thb */
pinfo->lcdc.h_pulse_width = 16; /* thpw */
pinfo->lcdc.v_front_porch = 4; /* tvfp */
pinfo->lcdc.v_back_porch = 4; /* tvb */
pinfo->lcdc.v_pulse_width = 4; /* tvpw */
pinfo->lcdc.border_clr = 0; /* black */
pinfo->lcdc.underflow_clr = 0xff; /* blue */
pinfo->lcdc.hsync_skew = 0;
/* Backlight levels - controled via PMIC pwm gpio */
pinfo->bl_max = 15;
pinfo->bl_min = 1;
/* mipi - general */
pinfo->mipi.vc = 0; /* virtual channel */
pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
pinfo->mipi.tx_eot_append = true;
pinfo->mipi.t_clk_post = 34; /* Calculated */
pinfo->mipi.t_clk_pre = 52; /* Calculated */
pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db;
/* Four lanes are recomended for 1280x800 at 60 frames per second */
pinfo->mipi.frame_rate = 60; /* 60 frames per second */
pinfo->mipi.data_lane0 = true;
pinfo->mipi.data_lane1 = true;
pinfo->mipi.data_lane2 = true;
pinfo->mipi.data_lane3 = true;
pinfo->mipi.mode = DSI_VIDEO_MODE;
/*
* Note: The CMI panel input is RGB888,
* thus the DSI-to-LVDS bridge output is RGB888.
* This parameter selects the DSI-Core output to the bridge.
*/
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
/* mipi - video mode */
pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT;
pinfo->mipi.pulse_mode_hsa_he = false; /* sync mode */
pinfo->mipi.hfp_power_stop = false;
pinfo->mipi.hbp_power_stop = false;
pinfo->mipi.hsa_power_stop = false;
pinfo->mipi.eof_bllp_power_stop = false;
pinfo->mipi.bllp_power_stop = false;
/* mipi - command mode */
pinfo->mipi.te_sel = 1; /* TE from vsycn gpio */
pinfo->mipi.interleave_max = 1;
/* The bridge supports only Generic Read/Write commands */
pinfo->mipi.insert_dcs_cmd = false;
pinfo->mipi.wr_mem_continue = 0;
pinfo->mipi.wr_mem_start = 0;
pinfo->mipi.stream = false; /* dma_p */
pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
//modify by pega Huimin
// pinfo->mipi.fixed_packet_size = 4;
pinfo->mipi.force_clk_lane_hs = 1;
ret = mipi_tc358764_dsi2lvds_register(pinfo, MIPI_DSI_PRIM,
MIPI_DSI_PANEL_WXGA);
if (ret)
pr_err("%s: failed to register device!\n", __func__);
return ret;
}
static int __init mipi_chimei_wuxga_init(void)
{
int ret;
struct msm_panel_info *pinfo = &chimei_wuxga_pinfo;
if (msm_fb_detect_client("mipi_video_chimei_wuxga"))
return 0;
pr_info("mipi-dsi chimei wuxga (1200x1920) driver ver 1.0.\n");
pinfo->xres = 1200;
pinfo->yres = 1920;
pinfo->type = MIPI_VIDEO_PANEL;
pinfo->pdest = DISPLAY_1;
pinfo->wait_cycle = 0;
pinfo->bpp = 24;
pinfo->fb_num = 2;
pinfo->clk_rate = 635 * MHZ ;
pinfo->lcdc.h_front_porch = 160-48-32;
pinfo->lcdc.h_back_porch = 48;
pinfo->lcdc.h_pulse_width = 32;
pinfo->lcdc.v_front_porch = 26-3-6;
pinfo->lcdc.v_back_porch = 3;
pinfo->lcdc.v_pulse_width = 6;
pinfo->lcdc.border_clr = 0;
pinfo->lcdc.underflow_clr = 0xff;
pinfo->lcdc.hsync_skew = 0;
pinfo->bl_max = PWM_LEVEL;
pinfo->bl_min = 1;
pinfo->mipi.vc = 0;
pinfo->mipi.rgb_swap = DSI_RGB_SWAP_RGB;
pinfo->mipi.tx_eot_append = true;
pinfo->mipi.t_clk_post = 34;
pinfo->mipi.t_clk_pre = 69;
pinfo->mipi.dsi_phy_db = &dsi_video_mode_phy_db;
pinfo->mipi.frame_rate = 60;
pinfo->mipi.data_lane0 = true;
pinfo->mipi.data_lane1 = true;
pinfo->mipi.data_lane2 = true;
pinfo->mipi.data_lane3 = true;
pinfo->mipi.esc_byte_ratio = 6;
pinfo->mipi.mode = DSI_VIDEO_MODE;
pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB565;
pinfo->mipi.traffic_mode = DSI_NON_BURST_SYNCH_EVENT;
pinfo->mipi.pulse_mode_hsa_he = false;
pinfo->mipi.hfp_power_stop = false;
pinfo->mipi.hbp_power_stop = false;
pinfo->mipi.hsa_power_stop = false;
pinfo->mipi.eof_bllp_power_stop = false;
pinfo->mipi.bllp_power_stop = false;
pinfo->mipi.te_sel = 1;
pinfo->mipi.interleave_max = 1;
pinfo->mipi.insert_dcs_cmd = false;
pinfo->mipi.wr_mem_continue = 0;
pinfo->mipi.wr_mem_start = 0;
pinfo->mipi.stream = false;
pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
pinfo->mipi.no_max_pkt_size = 1;
pinfo->mipi.force_clk_lane_hs = 1;
pinfo->is_3d_panel = FB_TYPE_3D_PANEL;
ret = mipi_tc358764_dsi2lvds_register(pinfo, MIPI_DSI_PRIM, 1);
if (ret)
pr_err("%s: failed to register device!\n", __func__);
return ret;
}
