void mips_cm_error_report(void) { u64 cm_error, cm_addr, cm_other; unsigned long revision; int ocause, cause; char buf[256]; if (!mips_cm_present()) return; revision = mips_cm_revision(); if (revision < CM_REV_CM3) { /* CM2 */ cm_error = read_gcr_error_cause(); cm_addr = read_gcr_error_addr(); cm_other = read_gcr_error_mult(); cause = cm_error >> CM_GCR_ERROR_CAUSE_ERRTYPE_SHF; ocause = cm_other >> CM_GCR_ERROR_MULT_ERR2ND_SHF; if (!cause) return; if (cause < 16) { unsigned long cca_bits = (cm_error >> 15) & 7; unsigned long tr_bits = (cm_error >> 12) & 7; unsigned long cmd_bits = (cm_error >> 7) & 0x1f; unsigned long stag_bits = (cm_error >> 3) & 15; unsigned long sport_bits = (cm_error >> 0) & 7; snprintf(buf, sizeof(buf), "CCA=%lu TR=%s MCmd=%s STag=%lu " "SPort=%lu\n", cca_bits, cm2_tr[tr_bits], cm2_cmd[cmd_bits], stag_bits, sport_bits); } else {
phys_addr_t __weak mips_cpc_phys_base(void) { u32 cpc_base; if (!mips_cm_present()) return 0; if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK)) return 0; /* If the CPC is already enabled, leave it so */ cpc_base = read_gcr_cpc_base(); if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK) return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK; /* Otherwise, give it the default address & enable it */ cpc_base = mips_cpc_default_phys_base(); write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK); return cpc_base; }
void __init arch_init_irq(void) { init_i8259_irqs(); if (!cpu_has_veic) mips_cpu_irq_init(); if (mips_cm_present()) { write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK); gic_present = 1; } else { if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; } }
/** * mips_cpc_phys_base - retrieve the physical base address of the CPC * * This function returns the physical base address of the Cluster Power * Controller memory mapped registers, or 0 if no Cluster Power Controller * is present. */ static phys_addr_t mips_cpc_phys_base(void) { unsigned long cpc_base; if (!mips_cm_present()) return 0; if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX)) return 0; /* If the CPC is already enabled, leave it so */ cpc_base = read_gcr_cpc_base(); if (cpc_base & CM_GCR_CPC_BASE_CPCEN) return cpc_base & CM_GCR_CPC_BASE_CPCBASE; /* Otherwise, use the default address */ cpc_base = mips_cpc_default_phys_base(); if (!cpc_base) return cpc_base; /* Enable the CPC, mapped at the default address */ write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN); return cpc_base; }
static int __init cps_pm_init(void) { unsigned cpu; int err; /* Detect appropriate sync types for the system */ switch (current_cpu_data.cputype) { case CPU_INTERAPTIV: case CPU_PROAPTIV: case CPU_M5150: case CPU_P5600: case CPU_I6400: stype_intervention = 0x2; stype_memory = 0x3; stype_ordering = 0x10; break; default: pr_warn("Power management is using heavyweight sync 0\n"); } /* A CM is required for all non-coherent states */ if (!mips_cm_present()) { pr_warn("pm-cps: no CM, non-coherent states unavailable\n"); goto out; } /* * If interrupts were enabled whilst running a wait instruction on a * non-coherent core then the VPE may end up processing interrupts * whilst non-coherent. That would be bad. */ if (cpu_wait == r4k_wait_irqoff) set_bit(CPS_PM_NC_WAIT, state_support); else pr_warn("pm-cps: non-coherent wait unavailable\n"); /* Detect whether a CPC is present */ if (mips_cpc_present()) { /* Detect whether clock gating is implemented */ if (read_cpc_cl_stat_conf() & CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK) set_bit(CPS_PM_CLOCK_GATED, state_support); else pr_warn("pm-cps: CPC does not support clock gating\n"); /* Power gating is available with CPS SMP & any CPC */ if (mips_cps_smp_in_use()) set_bit(CPS_PM_POWER_GATED, state_support); else pr_warn("pm-cps: CPS SMP not in use, power gating unavailable\n"); } else { pr_warn("pm-cps: no CPC, clock & power gating unavailable\n"); } for_each_present_cpu(cpu) { err = cps_gen_core_entries(cpu); if (err) return err; } out: return 0; }