static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t address) { struct mips_ejtag *ejtag_info = ctx->ejtag_info; int offset; uint32_t ejtag_ctrl, data; if ((address >= MIPS32_PRACC_PARAM_IN) && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) { offset = (address - MIPS32_PRACC_PARAM_IN) / 4; data = ctx->local_iparam[offset]; } else if ((address >= MIPS32_PRACC_PARAM_OUT) && (address <= MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) { offset = (address - MIPS32_PRACC_PARAM_OUT) / 4; data = ctx->local_oparam[offset]; } else if ((address >= MIPS32_PRACC_TEXT) && (address <= MIPS32_PRACC_TEXT + ctx->code_len * 4)) { offset = (address - MIPS32_PRACC_TEXT) / 4; data = ctx->code[offset]; } else if (address == MIPS32_PRACC_STACK) { /* save to our debug stack */ data = ctx->stack[--ctx->stack_offset]; } else { /* TODO: send JMP 0xFF200000 instruction. Hopefully processor jump back * to start of debug vector */ data = 0; LOG_ERROR("Error reading unexpected address 0x%8.8" PRIx32 "", address); return ERROR_JTAG_DEVICE_ERROR; } /* Send the data out */ mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_drscan_32(ctx->ejtag_info, &data); /* Clear the access pending bit (let the processor eat!) */ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl); jtag_add_clocks(5); jtag_execute_queue(); return ERROR_OK; }
int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info) { uint32_t ejtag_ctrl; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); if (ejtag_info->ejtag_version == EJTAG_VERSION_20) { LOG_INFO ("VERSION_20"); if (disable_dcr_mp(ejtag_info) != ERROR_OK) goto error; } /* set debug break bit */ ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK; LOG_DEBUG("Set Debug Break: ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* break bit will be cleared by hardware */ ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl); if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0) goto error; return ERROR_OK; error: LOG_ERROR("Failed to enter Debug Mode!"); return ERROR_FAIL; }
int mips_ejtag_drscan_38(struct mips_ejtag *ejtag_info, uint64_t *data) { struct jtag_tap *tap; tap = ejtag_info->tap; if (tap == NULL) return ERROR_FAIL; mips_ejtag_set_instr(ejtag_info, EJTAG_DCR_FDC); struct scan_field field; uint8_t t[5], r[5]; int retval; field.num_bits = 38; field.out_value = &t; buf_set_u64(t, 0, field.num_bits, *data); field.in_value = r; jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); retval = jtag_execute_queue(); if (retval != ERROR_OK) { LOG_ERROR("register read failed"); return retval; } *data = buf_get_u64(field.in_value, 0, 64); keep_alive(); return ERROR_OK; }
static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) { uint32_t ejtag_ctrl; long long then = timeval_ms(); int timeout; int retval; /* wait for the PrAcc to become "1" */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL); ejtag_ctrl = ejtag_info->ejtag_ctrl; while (1) { retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); if (retval != ERROR_OK) return retval; if (ejtag_ctrl & EJTAG_CTRL_PRACC) break; timeout = timeval_ms() - then; if (timeout > 1000) { LOG_DEBUG("DEBUGMODULE: No memory access in progress!"); return ERROR_JTAG_DEVICE_ERROR; } } *ctrl = ejtag_ctrl; return ERROR_OK; }
static int ejtag_dma_read_h(mips_ejtag_t *ejtag_info, u32 addr, u16 *data) { u32 v; u32 ejtag_ctrl; int retries = RETRY_ATTEMPTS; begin_ejtag_dma_read_h: /* Setup Address */ v = addr; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_drscan_32(ejtag_info, &v); /* Initiate DMA Read & set DSTRT */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); /* Wait for DSTRT to Clear */ do { ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); } while(ejtag_ctrl & EJTAG_CTRL_DSTRT); /* Read Data */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_drscan_32(ejtag_info, &v); /* Clear DMA & Check DERR */ mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); if (ejtag_ctrl & EJTAG_CTRL_DERR) { if (retries--) { LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ (retrying)\n", addr); goto begin_ejtag_dma_read_h; } else LOG_ERROR("DMA Read Addr = %08x Data = ERROR ON READ\n", addr); return ERROR_JTAG_DEVICE_ERROR; } /* Handle the bigendian/littleendian */ if (addr & 0x2) *data = (v >> 16) & 0xffff; else
static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t address) { uint32_t ejtag_ctrl,data; int offset; struct mips_ejtag *ejtag_info = ctx->ejtag_info; int retval; mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA); retval = mips_ejtag_drscan_32(ctx->ejtag_info, &data); if (retval != ERROR_OK) return retval; /* Clear access pending bit */ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL); mips_ejtag_drscan_32_out(ctx->ejtag_info, ejtag_ctrl); retval = jtag_execute_queue(); if (retval != ERROR_OK) return retval; if ((address >= MIPS32_PRACC_PARAM_IN) && (address <= MIPS32_PRACC_PARAM_IN + ctx->num_iparam * 4)) { offset = (address - MIPS32_PRACC_PARAM_IN) / 4; ctx->local_iparam[offset] = data; } else if ((address >= MIPS32_PRACC_PARAM_OUT) && (address <= MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4)) { offset = (address - MIPS32_PRACC_PARAM_OUT) / 4; ctx->local_oparam[offset] = data; } else if (address == MIPS32_PRACC_STACK) { /* save data onto our stack */ ctx->stack[ctx->stack_offset++] = data; } else { LOG_ERROR("Error writing unexpected address 0x%8.8" PRIx32 "", address); return ERROR_JTAG_DEVICE_ERROR; } return ERROR_OK; }
int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_t *code, int num_param_in, uint32_t *param_in, int num_param_out, uint32_t *param_out, int cycle) { uint32_t ejtag_ctrl; uint32_t address, data; struct mips32_pracc_context ctx; int retval; int pass = 0; ctx.local_iparam = param_in; ctx.local_oparam = param_out; ctx.num_iparam = num_param_in; ctx.num_oparam = num_param_out; ctx.code = code; ctx.code_len = code_len; ctx.ejtag_info = ejtag_info; ctx.stack_offset = 0; while (1) { if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) return retval; address = data = 0; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_drscan_32(ejtag_info, &address); /* Check for read or write */ if (ejtag_ctrl & EJTAG_CTRL_PRNW) { if ((retval = mips32_pracc_exec_write(&ctx, address)) != ERROR_OK) return retval; } else { /* Check to see if its reading at the debug vector. The first pass through * the module is always read at the vector, so the first one we allow. When * the second read from the vector occurs we are done and just exit. */ if ((address == MIPS32_PRACC_TEXT) && (pass++)) { break; } if ((retval = mips32_pracc_exec_read(&ctx, address)) != ERROR_OK) return retval; } if (cycle == 0) break; } /* stack sanity check */ if (ctx.stack_offset != 0) { LOG_DEBUG("Pracc Stack not zero"); } return ERROR_OK; }
static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl) { uint32_t ejtag_ctrl; while (1) { mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); ejtag_ctrl = ejtag_info->ejtag_ctrl; mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); if (ejtag_ctrl & EJTAG_CTRL_PRACC) break; LOG_DEBUG("DEBUGMODULE: No memory access in progress!\n"); return ERROR_JTAG_DEVICE_ERROR; } *ctrl = ejtag_ctrl; return ERROR_OK; }
//static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode) int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode) { struct scan_field field; uint8_t r[4]; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE); field.num_bits = 32; field.out_value = NULL; field.in_value = r; jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE); int retval; retval = jtag_execute_queue(); if (retval != ERROR_OK) { LOG_ERROR("register read failed"); return retval; } *impcode = buf_get_u32(field.in_value, 0, 32); return ERROR_OK; }
/* fastdata upload/download requires an initialized working area * to load the download code; it should not be called otherwise * fetch order from the fastdata area * 1. start addr * 2. end addr * 3. data ... */ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source, int write, uint32_t addr, int count, uint32_t *buf) { uint32_t handler_code[] = { /* caution when editing, table is modified below */ /* r15 points to the start of this code */ MIPS32_SW(8,MIPS32_FASTDATA_HANDLER_SIZE - 4,15), MIPS32_SW(9,MIPS32_FASTDATA_HANDLER_SIZE - 8,15), MIPS32_SW(10,MIPS32_FASTDATA_HANDLER_SIZE - 12,15), MIPS32_SW(11,MIPS32_FASTDATA_HANDLER_SIZE - 16,15), /* start of fastdata area in t0 */ MIPS32_LUI(8,UPPER16(MIPS32_PRACC_FASTDATA_AREA)), MIPS32_ORI(8,8,LOWER16(MIPS32_PRACC_FASTDATA_AREA)), MIPS32_LW(9,0,8), /* start addr in t1 */ MIPS32_LW(10,0,8), /* end addr to t2 */ /* loop: */ /* 8 */ MIPS32_LW(11,0,0), /* lw t3,[t8 | r9] */ /* 9 */ MIPS32_SW(11,0,0), /* sw t3,[r9 | r8] */ MIPS32_BNE(10,9,NEG16(3)), /* bne $t2,t1,loop */ MIPS32_ADDI(9,9,4), /* addi t1,t1,4 */ MIPS32_LW(8,MIPS32_FASTDATA_HANDLER_SIZE - 4,15), MIPS32_LW(9,MIPS32_FASTDATA_HANDLER_SIZE - 8,15), MIPS32_LW(10,MIPS32_FASTDATA_HANDLER_SIZE - 12,15), MIPS32_LW(11,MIPS32_FASTDATA_HANDLER_SIZE - 16,15), MIPS32_LUI(15,UPPER16(MIPS32_PRACC_TEXT)), MIPS32_ORI(15,15,LOWER16(MIPS32_PRACC_TEXT)), MIPS32_JR(15), /* jr start */ MIPS32_MFC0(15,31,0), /* move COP0 DeSave to $15 */ }; uint32_t jmp_code[] = { MIPS32_MTC0(15,31,0), /* move $15 to COP0 DeSave */ /* 1 */ MIPS32_LUI(15,0), /* addr of working area added below */ /* 2 */ MIPS32_ORI(15,15,0), /* addr of working area added below */ MIPS32_JR(15), /* jump to ram program */ MIPS32_NOP, }; int retval, i; uint32_t val, ejtag_ctrl, address; if (source->size < MIPS32_FASTDATA_HANDLER_SIZE) return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; if (write) { handler_code[8] = MIPS32_LW(11,0,8); /* load data from probe at fastdata area */ handler_code[9] = MIPS32_SW(11,0,9); /* store data to RAM @ r9 */ } else { handler_code[8] = MIPS32_LW(11,0,9); /* load data from RAM @ r9 */ handler_code[9] = MIPS32_SW(11,0,8); /* store data to probe at fastdata area */ } /* write program into RAM */ mips32_pracc_write_mem32(ejtag_info, source->address, ARRAY_SIZE(handler_code), handler_code); LOG_DEBUG("%s using 0x%.8" PRIx32 " for write handler\n", __func__, source->address); jmp_code[1] |= UPPER16(source->address); jmp_code[2] |= LOWER16(source->address); for (i = 0; i < (int) ARRAY_SIZE(jmp_code); i++) { if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) return retval; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL); mips_ejtag_drscan_32(ejtag_info, &jmp_code[i]); /* Clear the access pending bit (let the processor eat!) */ ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); } if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) return retval; /* next fetch to dmseg should be in FASTDATA_AREA, check */ address = 0; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_drscan_32(ejtag_info, &address); if (address != MIPS32_PRACC_FASTDATA_AREA) return ERROR_FAIL; /* Send the load start address */ val = addr; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL); mips_ejtag_fastdata_scan(ejtag_info, 1, &val); /* Send the load end address */ val = addr + (count - 1) * 4; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL); mips_ejtag_fastdata_scan(ejtag_info, 1, &val); for (i = 0; i < count; i++) { /* Send the data out using fastdata (clears the access pending bit) */ if ((retval = mips_ejtag_fastdata_scan(ejtag_info, write, buf++)) != ERROR_OK) return retval; } if ((retval = jtag_execute_queue()) != ERROR_OK) { LOG_ERROR("fastdata load failed"); return retval; } if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK) return retval; address = 0; mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL); mips_ejtag_drscan_32(ejtag_info, &address); if (address != MIPS32_PRACC_TEXT) LOG_ERROR("mini program did not return to start\n"); return retval; }