void mips_isa_BNE_impl(struct mips_ctx_t *ctx) {
if (mips_gpr_get_value(ctx, RS) != mips_gpr_get_value(ctx, RT)) {
mips_isa_rel_branch(ctx, SEXT32(IMM << 2, 16));
mips_isa_inst_debug(" Branch taken");
} else
mips_isa_inst_debug(" Branch not taken");
}
void mips_isa_LW_impl(struct mips_ctx_t *ctx)
{
unsigned int temp;
unsigned int addr = mips_gpr_get_value(ctx,RS) + SEXT32((signed)IMM,16);
if ((BITS32(addr, 1, 0) | 0) == 1 )
fatal("LW: address error, effective address must be naturallty-aligned\n");
mem_read(ctx->mem, addr, 4, &temp);
mips_gpr_set_value(ctx,RT, temp);
mips_isa_inst_debug(" $0x%x=>tmp0, tmp0+r%d=>tmp0, tmp0=>r%d\n", SEXT32(IMM,16), RS, RT);
mips_isa_inst_debug(" value loaded: %x", temp);
}
void mips_isa_BEQ_impl(struct mips_ctx_t *ctx)
{
if (mips_gpr_get_value(ctx,RS) == mips_gpr_get_value(ctx,RT))
mips_isa_rel_branch(ctx,SEXT32(IMM << 2,16));
//mips_isa_rel_branch(ctx,SEXT32(SEXT32(IMM,16) << 2, 18));
mips_isa_inst_debug(" regRS = %d and regRT = %d", mips_gpr_get_value(ctx,RS), mips_gpr_get_value(ctx,RT));
}
void mips_isa_SB_impl(struct mips_ctx_t *ctx)
{
unsigned char temp = mips_gpr_get_value(ctx,RT);
unsigned int addr = mips_gpr_get_value(ctx,RS) + IMM;
mem_write(ctx->mem, addr, sizeof(unsigned char), &temp);
mips_isa_inst_debug("byte written: %x",temp);
}
void mips_isa_SW_impl(struct mips_ctx_t *ctx) {
unsigned int temp = mips_gpr_get_value(ctx, RT);
unsigned int addr = mips_gpr_get_value(ctx, RS) + SEXT32(IMM, 16);
mem_write(ctx->mem, addr, 4, &temp);
mips_isa_inst_debug(" value stored: 0x%x", temp);
}
void mips_isa_LBU_impl(struct mips_ctx_t *ctx) {
unsigned char temp;
unsigned int addr = mips_gpr_get_value(ctx, RS) + SEXT32(IMM, 16);
mem_read(ctx->mem, addr, sizeof(unsigned char), &temp);
mips_gpr_set_value(ctx, RT, (unsigned)temp);
mips_isa_inst_debug(" r%d=0x%x", RT, mips_gpr_get_value(ctx, RT));
}
void mips_isa_ADDI_impl(struct mips_ctx_t *ctx)
{
int temp;
temp = (int)mips_gpr_get_value(ctx,RS) + (int)(OFFSET);
mips_gpr_set_value(ctx,RT, temp);
mips_isa_inst_debug(" r%d -> 0x%x", RT, temp);
}
/* FIXME - merge with ctx_execute */
void mips_isa_execute_inst(struct mips_ctx_t *ctx) {
// struct mips_regs_t *regs = ctx->regs;
ctx->next_ip = ctx->n_next_ip;
ctx->n_next_ip += 4;
/* Debug */
if (debug_status(mips_isa_inst_debug_category)) {
mips_isa_inst_debug("%d %8lld %x: ", ctx->pid,
asEmu(mips_emu)->instructions, ctx->regs->pc);
mips_inst_debug_dump(&ctx->inst, debug_file(mips_isa_inst_debug_category));
}
/* Call instruction emulation function */
// regs->pc = regs->pc + ctx->inst.info->size;
if (ctx->inst.info->opcode) mips_isa_inst_func[ctx->inst.info->opcode](ctx);
/* Statistics */
mips_inst_freq[ctx->inst.info->opcode]++;
/* Debug */
mips_isa_inst_debug("\n");
// if (debug_status(mips_isa_call_debug_category))
// mips_isa_debug_call(ctx);
}
void mips_isa_ADDIU_impl(struct mips_ctx_t *ctx)
{
mips_gpr_set_value(ctx,RT, mips_gpr_get_value(ctx,RS) + SEXT32((signed)IMM, 16));
mips_isa_inst_debug(" r%d -> r%d+0x%x", RT, RS, SEXT32(IMM, 16));
}
void mips_isa_SLL_impl(struct mips_ctx_t *ctx)
{
mips_gpr_set_value(ctx,RD, (mips_gpr_get_value(ctx,RT) << SA));
mips_isa_inst_debug(" %x=%x<<%x", mips_gpr_get_value(ctx,RD), mips_gpr_get_value(ctx,RT), SA);
}
void mips_isa_LUI_impl(struct mips_ctx_t *ctx)
{
mips_gpr_set_value(ctx,RT, (int)(IMM << 16));
mips_isa_inst_debug(" r%d: $0x%x", RT, mips_gpr_get_value(ctx,RT));
}
void mips_isa_ORI_impl(struct mips_ctx_t *ctx)
{
mips_gpr_set_value(ctx,RT, mips_gpr_get_value(ctx,RS) | ((unsigned int) (IMM) & ((1U << (16)) - 1)));
// (unsigned int) IMM);
mips_isa_inst_debug(" r%d=0x%x", RT, mips_gpr_get_value(ctx,RT));
}
