/* * Low-level read and write register routines; the Altera UART is little * endian, so we byte swap 32-bit reads and writes. */ static inline uint32_t uart_data_read(void) { return (mips_ioread_uint32le(mips_phys_to_uncached(CHERI_UART_BASE + ALTERA_JTAG_UART_DATA_OFF))); }
static inline uint32_t uart_control_read(void) { return (mips_ioread_uint32le(mips_phys_to_uncached(CHERI_UART_BASE + ALTERA_JTAG_UART_CONTROL_OFF))); }
static inline void uart_control_write(uint32_t v) { mips_iowrite_uint32le(mips_phys_to_uncached(CHERI_UART_BASE + ALTERA_JTAG_UART_DATA_OFF), v); }
void hw_reboot(void) { #ifdef HARDWARE_qemu /* Used to quit Qemu */ mips_iowrite_uint8(mips_phys_to_uncached(0x1f000000 + 0x00500), 0x42); #endif for(;;); }