static int pmb_seq_show(struct seq_file *file, void *iter) { int i; seq_printf(file, "V: Valid, C: Cacheable, WT: Write-Through\n" "CB: Copy-Back, B: Buffered, UB: Unbuffered\n"); seq_printf(file, "ety vpn ppn size flags\n"); for (i = 0; i < NR_PMB_ENTRIES; i++) { unsigned long addr, data; unsigned int size; char *sz_str = NULL; addr = ctrl_inl(mk_pmb_addr(i)); data = ctrl_inl(mk_pmb_data(i)); size = data & PMB_SZ_MASK; sz_str = (size == PMB_SZ_16M) ? " 16MB": (size == PMB_SZ_64M) ? " 64MB": (size == PMB_SZ_128M) ? "128MB": "512MB"; /* 02: V 0x88 0x08 128MB C CB B */ seq_printf(file, "%02d: %c 0x%02lx 0x%02lx %s %c %s %s\n", i, ((addr & PMB_V) && (data & PMB_V)) ? 'V' : ' ', (addr >> 24) & 0xff, (data >> 24) & 0xff, sz_str, (data & PMB_C) ? 'C' : ' ', (data & PMB_WT) ? "WT" : "CB", (data & PMB_UB) ? "UB" : " B"); } return 0; }
void __uses_jump_to_uncached clear_pmb_entry(struct pmb_entry *pmbe) { unsigned int entry = pmbe->entry; unsigned long addr; /* * Don't allow clearing of wired init entries, P1 or P2 access * without a corresponding mapping in the PMB will lead to reset * by the TLB. */ if (unlikely(entry < ARRAY_SIZE(pmb_init_map) || entry >= NR_PMB_ENTRIES)) return; jump_to_uncached(); /* Clear V-bit */ addr = mk_pmb_addr(entry); ctrl_outl(ctrl_inl(addr) & ~PMB_V, addr); addr = mk_pmb_data(entry); ctrl_outl(ctrl_inl(addr) & ~PMB_V, addr); back_to_cached(); clear_bit(entry, &pmb_map); }
/* * Must be in P2 for __set_pmb_entry() */ int __set_pmb_entry(unsigned long vpn, unsigned long ppn, unsigned long flags, int *entry) { unsigned int pos = *entry; if (unlikely(pos == PMB_NO_ENTRY)) pos = find_first_zero_bit(&pmb_map, NR_PMB_ENTRIES); repeat: if (unlikely(pos > NR_PMB_ENTRIES)) return -ENOSPC; if (test_and_set_bit(pos, &pmb_map)) { pos = find_first_zero_bit(&pmb_map, NR_PMB_ENTRIES); goto repeat; } ctrl_outl(vpn | PMB_V, mk_pmb_addr(pos)); #ifdef CONFIG_CACHE_WRITETHROUGH /* * When we are in 32-bit address extended mode, CCR.CB becomes * invalid, so care must be taken to manually adjust cacheable * translations. */ if (likely(flags & PMB_C)) flags |= PMB_WT; #endif ctrl_outl(ppn | flags | PMB_V, mk_pmb_data(pos)); *entry = pos; return 0; }
static void __clear_pmb_entry(struct pmb_entry *pmbe) { unsigned long addr, data; unsigned long addr_val, data_val; addr = mk_pmb_addr(pmbe->entry); data = mk_pmb_data(pmbe->entry); addr_val = __raw_readl(addr); data_val = __raw_readl(data); /* Clear V-bit */ writel_uncached(addr_val & ~PMB_V, addr); writel_uncached(data_val & ~PMB_V, data); }
/* * Sync our software copy of the PMB mappings with those in hardware. The * mappings in the hardware PMB were either set up by the bootloader or * very early on by the kernel. */ static void __init pmb_synchronize(void) { struct pmb_entry *pmbp = NULL; int i, j; /* * Run through the initial boot mappings, log the established * ones, and blow away anything that falls outside of the valid * PPN range. Specifically, we only care about existing mappings * that impact the cached/uncached sections. * * Note that touching these can be a bit of a minefield; the boot * loader can establish multi-page mappings with the same caching * attributes, so we need to ensure that we aren't modifying a * mapping that we're presently executing from, or may execute * from in the case of straddling page boundaries. * * In the future we will have to tidy up after the boot loader by * jumping between the cached and uncached mappings and tearing * down alternating mappings while executing from the other. */ for (i = 0; i < NR_PMB_ENTRIES; i++) { unsigned long addr, data; unsigned long addr_val, data_val; unsigned long ppn, vpn, flags; unsigned long irqflags; unsigned int size; struct pmb_entry *pmbe; addr = mk_pmb_addr(i); data = mk_pmb_data(i); addr_val = __raw_readl(addr); data_val = __raw_readl(data); /* * Skip over any bogus entries */ if (!(data_val & PMB_V) || !(addr_val & PMB_V)) continue; ppn = data_val & PMB_PFN_MASK; vpn = addr_val & PMB_PFN_MASK; /* * Only preserve in-range mappings. */ if (!pmb_ppn_in_range(ppn)) { /* * Invalidate anything out of bounds. */ writel_uncached(addr_val & ~PMB_V, addr); writel_uncached(data_val & ~PMB_V, data); continue; } /* * Update the caching attributes if necessary */ if (data_val & PMB_C) { data_val &= ~PMB_CACHE_MASK; data_val |= pmb_cache_flags(); writel_uncached(data_val, data); } size = data_val & PMB_SZ_MASK; flags = size | (data_val & PMB_CACHE_MASK); pmbe = pmb_alloc(vpn, ppn, flags, i); if (IS_ERR(pmbe)) { WARN_ON_ONCE(1); continue; } spin_lock_irqsave(&pmbe->lock, irqflags); for (j = 0; j < ARRAY_SIZE(pmb_sizes); j++) if (pmb_sizes[j].flag == size) pmbe->size = pmb_sizes[j].size; if (pmbp) { spin_lock(&pmbp->lock); /* * Compare the previous entry against the current one to * see if the entries span a contiguous mapping. If so, * setup the entry links accordingly. Compound mappings * are later coalesced. */ if (pmb_can_merge(pmbp, pmbe)) pmbp->link = pmbe; spin_unlock(&pmbp->lock); } pmbp = pmbe; spin_unlock_irqrestore(&pmbe->lock, irqflags); } }
/* * Must be run uncached. */ static void __set_pmb_entry(struct pmb_entry *pmbe) { writel_uncached(pmbe->vpn | PMB_V, mk_pmb_addr(pmbe->entry)); writel_uncached(pmbe->ppn | pmbe->flags | PMB_V, mk_pmb_data(pmbe->entry)); }