int GPIORelaisController::openMap()
{
int res = 1;
info_printf("GPIORelaisController::openMap\n");
gpioregs = (char *) mmap_device_memory( 0, gpioPortLen, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, gpioPortBase );
if ( gpioregs == MAP_FAILED ) {
info_printf( "mmap_device_memory for physical address %X and length %X failed\n", gpioPortBase, gpioPortLen );
res = 0;
}
/* memfd = open("/dev/mem", O_RDWR|O_SYNC);
if( memfd == NULL ) {
info_printf("Error while opening the mem file.\n");
gpioregs = MAP_FAILED;
res = 0;
}
if (res == 0 ) {
gpioregs = (char *)mmap(0, mapLen, PROT_READ|PROT_WRITE, MAP_SHARED, memfd, mapBase);
if (gpioregs == MAP_FAILED) {
info_printf("Error while mmap.\n");
res = 0;
}
// info_printf("gpioregs mapped\n");
}
// usleep(500000);
*/
return res;
}
_X_EXPORT int
xf86ReadBIOS(unsigned long Base, unsigned long Offset, unsigned char *Buf,
int Len)
{
unsigned char *ptr;
int psize;
int mlen;
psize = xf86getpagesize();
Offset += Base & (psize - 1);
Base &= ~(psize - 1);
mlen = (Offset + Len + psize - 1) & ~(psize - 1);
ptr = (unsigned char *)mmap_device_memory((caddr_t)0, mlen, PROT_READ,
0, (off_t)Base);
if ((long)ptr == -1)
{
xf86Msg(X_WARNING,
"xf86ReadBIOS: %s mmap[s=%x,a=%lx,o=%lx] failed (%s)\n",
DEV_MEM, Len, Base, Offset, strerror(errno));
return(-1);
}
#ifdef DEBUG
ErrorF("xf86ReadBIOS: BIOS at 0x%08x has signature 0x%04x\n",
Base, ptr[0] | (ptr[1] << 8));
#endif
(void)memcpy(Buf, (void *)(ptr + Offset), Len);
(void)munmap_device_memory((caddr_t)ptr, mlen);
#ifdef DEBUG
xf86MsgVerb(X_INFO, 3, "xf86ReadBIOS(%x, %x, Buf, %x)"
"-> %02x %02x %02x %02x...\n",
Base, Offset, Len, Buf[0], Buf[1], Buf[2], Buf[3]);
#endif
return(Len);
}
static int bochs_init(struct pci_slot_dev *pci_dev) {
int ret;
struct fb_info *info;
size_t mmap_len;
assert(pci_dev != NULL);
info = fb_alloc();
if (info == NULL) {
return -ENOMEM;
}
memcpy(&info->fix, &bochs_fix_screeninfo, sizeof info->fix);
fill_var(&info->var);
info->ops = &bochs_ops;
info->screen_base = (void *)(pci_dev->bar[0] & ~0xf); /* FIXME */
mmap_len = binalign_bound(VBE_DISPI_MAX_XRES * VBE_DISPI_MAX_YRES * VBE_DISPI_MAX_BPP / 8, PAGE_SIZE());
if (MAP_FAILED == mmap_device_memory(info->screen_base,
mmap_len,
PROT_READ|PROT_WRITE|PROT_NOCACHE,
MAP_FIXED,
(unsigned long) info->screen_base)) {
return -EIO;
}
ret = fb_register(info);
if (ret != 0) {
fb_release(info);
return ret;
}
return 0;
}
int32_t
omap3530_sdma_attach(omap3530_spi_t *omap3530)
{
int tx_idx = omap3530->sdma_tx_chid = -1;
int rx_idx = omap3530->sdma_rx_chid = -1;
rsrc_request_t req = { 0 };
/* Map in DMA registers */
if ((omap3530->dma4 = mmap_device_memory (0, sizeof (dma4_t),
PROT_READ | PROT_WRITE | PROT_NOCACHE, 0, DMA4_BASE_ADDR)) == MAP_FAILED)
{
fprintf(stderr, "Unable to mmap DMA (%s) \n", strerror (errno));
return (-1);
}
/*
*********** SPI: transmit ****************
*/
req.length = 1;
req.flags = RSRCDBMGR_DMA_CHANNEL;
if (rsrcdbmgr_attach (&req, 1) == -1)
{
fprintf(stderr, "Unable to aquire DMA channels (%s) \n", strerror (errno));
munmap_device_memory (omap3530->dma4, sizeof (dma4_t));
return (-1);
}
tx_idx = omap3530->sdma_tx_chid = req.start;
/*
*********** SPI: receive ****************
*/
memset (&req, 0, sizeof (req));
req.length = 1;
req.flags = RSRCDBMGR_DMA_CHANNEL;
if (rsrcdbmgr_attach (&req, 1) == -1)
{
fprintf(stderr, "Unable to aquire DMA channels (%s) \n", strerror (errno));
omap3530_sdma_detach (omap3530);
return (-1);
}
rx_idx = omap3530->sdma_rx_chid = req.start;
// do some common initiailization
omap3530->dma4->channel[tx_idx].cse = 1;
omap3530->dma4->channel[tx_idx].cde = 1;
omap3530->dma4->channel[rx_idx].cse = 1;
omap3530->dma4->channel[rx_idx].cde = 1;
omap3530->dma4->channel[tx_idx].cdf = 0;
omap3530->dma4->channel[rx_idx].csf = 0;
omap3530->dma4->channel[tx_idx].csdp = DMA4_CSDP_DATA_TYPE_8BIT;
omap3530->dma4->channel[rx_idx].csdp = DMA4_CSDP_DATA_TYPE_8BIT;
return 0;
}
static int ns16550_init(void) {
/* Map one vmem page to handle this device if mmu is used */
mmap_device_memory(
(void*) (COM_BASE & ~MMU_PAGE_MASK),
PROT_READ | PROT_WRITE | PROT_NOCACHE,
binalign_bound(sizeof (struct com), MMU_PAGE_SIZE),
MAP_FIXED,
COM_BASE & ~MMU_PAGE_MASK
);
return 0;
}
static int omap_clk_init(void) {
/* Map one vmem page to handle this device if mmu is used */
mmap_device_memory(
(void*) ((uintptr_t) GPTIMER1_BASE & ~MMU_PAGE_MASK),
PROT_READ | PROT_WRITE | PROT_NOCACHE,
binalign_bound(sizeof(struct gptimerxx_x), MMU_PAGE_SIZE),
VMEM_PAGE_WRITABLE,
((uintptr_t) GPTIMER1_BASE & ~MMU_PAGE_MASK)
);
clock_source_register(&omap3_clk_clock_source);
return irq_attach(GPTIMER1_IRQ, clock_handler, 0, &omap3_clk_clock_source, "omap3_clk");
}
static int omap3_intc_init(void) {
/* Map one vmem page to handle this device if mmu is used */
mmap_device_memory(
(void*) (OMAP35X_INTC_BASE & ~MMU_PAGE_MASK),
PROT_READ | PROT_WRITE | PROT_NOCACHE,
binalign_bound(
OMAP35X_INTC_ILR(__IRQCTRL_IRQS_TOTAL) - OMAP35X_INTC_BASE,
MMU_PAGE_MASK),
MAP_FIXED,
OMAP35X_INTC_BASE & ~MMU_PAGE_MASK
);
return 0;
}
static pointer
mapVidMem(int ScreenNum, unsigned long Base, unsigned long Size, int flags)
{
pointer base;
base = mmap_device_memory (0, Size, (flags & VIDMEM_READONLY) ?
PROT_READ : (PROT_READ | PROT_WRITE), 0, (uint64_t)Base);
if (base == MAP_FAILED)
{
FatalError("%s: could not mmap %s [s=%lx,a=%lx] (%s)",
"xf86MapVidMem", DEV_MEM, Size, Base,
strerror(errno));
}
return(base);
}
static int this_init(void) {
/* Map one vmem page to handle this device if mmu is used */
mmap_device_memory(
(void*) ((uintptr_t) BCM2835_SYSTEM_TIMER_BASE & ~MMU_PAGE_MASK),
PROT_READ | PROT_WRITE | PROT_NOCACHE,
binalign_bound(sizeof(struct raspi_timer_regs), MMU_PAGE_SIZE),
MAP_FIXED,
((uintptr_t) BCM2835_SYSTEM_TIMER_BASE & ~MMU_PAGE_MASK)
);
clock_source_register(&this_clock_source);
irq_attach(SYSTICK_IRQ, clock_handler, 0, &this_clock_source,
"Raspberry PI systick timer");
return 0;
}
/*
* Function - __pwm_setup()
*
* Arguments - None
*
* Return Value - None
*/
static __inline void __pwm_setup(void)
{
timer_t timer_id;
struct sigevent event;
struct itimerspec interval_time;
// Set-up signal handler for handling __SIG_SETUP_OP
action.sa_handler = __pwm_signal_handler;
action.sa_flags = SA_SIGINFO;
sigaction(__SIG_SETUP_OP, &action, NULL);
#if defined (__ARM__)
// Map GPIO address into virtual memory
gpio_base = (sint32_t)mmap_device_memory(0,
GPIO_MEM_SIZE,
(PROT_READ | PROT_WRITE | PROT_NOCACHE),
0,
(uint32_t)GPIO_BASE_ADDR);
if(gpio_base == MAP_DEVICE_FAILED)
{
perror("Mapping GPIO base address\n");
exit(0);
}
#endif // #if defined (__ARM__)
// Create channel for timer pulses
channel_id = ChannelCreate(0);
// Setup timer pulse event
event.sigev_notify = SIGEV_PULSE;
event.sigev_priority = getprio(0);
event.sigev_code = __TIMER_PULSE_CODE;
event.sigev_coid = ConnectAttach(ND_LOCAL_NODE, 0, channel_id, _NTO_SIDE_CHANNEL, 0);
// Create the timer
timer_create(CLOCK_REALTIME, &event, &timer_id);
// Set timer interval
interval_time.it_value.tv_sec = 0;
interval_time.it_value.tv_nsec = __TIMER_TICK_NS;
interval_time.it_interval.tv_sec = 0;
interval_time.it_interval.tv_nsec = __TIMER_TICK_NS;
// Timer will start after this call
timer_settime(timer_id, 0, &interval_time, NULL);
}
int main(int argc, char **argv)
{
unsigned int base_addr = 0xd8000; // truck CAN 1 address
unsigned char reg_addr;
unsigned char value;
unsigned int pbase;
unsigned int mask = 0xffffffff; // print all by default
unsigned char data_mask = 0xff; // use complete value by default
volatile unsigned char *preg;
int i;
ThreadCtl(_NTO_TCTL_IO, NULL); //required to access I/O ports
printf("array size %d\n", array_size);
if (argc > 1)
sscanf(argv[1],"%i",&base_addr);
if (argc > 2)
sscanf(argv[2], "%i", &mask);
if (argc > 3)
sscanf(argv[3], "%hhi", &data_mask);
printf("base 0x%08x, mask 0x%08x, data_mask 0x%02x\n",
base_addr, mask, data_mask);
pbase = (unsigned int) mmap_device_memory(NULL,
I82527_MAP_SIZE,
PROT_READ | PROT_WRITE | PROT_NOCACHE,
0, base_addr);
printf("Mapped address 0x%08x\n", pbase);
for (i = 0; i < array_size; i++) {
if ((mask & (1 << i)) == 0)
continue;
reg_addr = init_array[i].addr;
value = init_array[i].value & data_mask;
preg = (volatile unsigned char *) (pbase + reg_addr);
*preg = value;
printf("0x%02x: wrote 0x%02x\n", reg_addr, value);
}
return 0;
}
static int cirrus_init(struct pci_slot_dev *pci_dev) {
char *mmap_base = (char *)(pci_dev->bar[0] & PCI_BASE_ADDR_IO_MASK); /* FIXME */
size_t mmap_len = 1024 * 1280 * 16 / 8;
struct fb_info *info;
if (MAP_FAILED == mmap_device_memory(mmap_base,
mmap_len,
PROT_READ|PROT_WRITE|PROT_NOCACHE,
MAP_FIXED,
(unsigned long) mmap_base)) {
return -EIO;
}
info = fb_create(&cl_ops, mmap_base, mmap_len);
if (info == NULL) {
munmap(mmap_base, mmap_len);
return -ENOMEM;
}
return 0;
}
static int
handleNeutrinoJxeSpaceArg(J9PortLibrary * portLib, int jxeSpaceArg, char **argv)
{
PORT_ACCESS_FROM_PORT(portLib);
char *tmpargv = &argv[jxeSpaceArg][10];
char *partitionStr = NULL;
char *virtStr = NULL;
int correctParms = 0;
U_32 physicalAddr = 0;
U_32 jxeSpaceSize = 0;
void *logicalAddr = NULL;
void *mappedAddr = NULL;
/* parse out the jxespace options, all parameters are expected to be hex */
physicalAddr = parseStringToLong(tmpargv);
partitionStr = strchr(tmpargv, ',');
if (partitionStr) {
jxeSpaceSize = parseStringToLong(partitionStr + 1);
correctParms = 1;
virtStr = strchr(partitionStr + 1, ',');
if (virtStr) {
logicalAddr = (void *) parseStringToLong(virtStr + 1);
}
}
/* Don't continue if parsing failed or requested size is 0 */
if (!correctParms || !jxeSpaceSize) {
j9nls_printf(PORTLIB, J9NLS_ERROR, J9NLS_EXE_INVALID_JXESPACE ); /* \nInvalid jxespace parameters.\n */
return 8;
}
/* Get the logical mapped addr. */
mappedAddr = mmap_device_memory(logicalAddr, jxeSpaceSize, PROT_READ | PROT_NOCACHE, 0, physicalAddr);
if (mappedAddr == MAP_FAILED) {
j9nls_printf( PORTLIB, J9NLS_ERROR, J9NLS_EXE_ERROR_MAPPING_JXE_IN_FLASH ); /* \nError mapping jxe in flash\n */
return 7;
}
return 0;
}
static int bochs_init(struct pci_slot_dev *pci_dev) {
char *mmap_base = (char *)(pci_dev->bar[0] & ~0xf); /* FIXME */
size_t mmap_len = binalign_bound(VBE_DISPI_MAX_XRES
* VBE_DISPI_MAX_YRES
* VBE_DISPI_MAX_BPP / 8, PAGE_SIZE());
struct fb_info *info;
if (MAP_FAILED == mmap_device_memory(mmap_base,
mmap_len,
PROT_READ|PROT_WRITE|PROT_NOCACHE,
MAP_FIXED,
(unsigned long) mmap_base)) {
return -EIO;
}
info = fb_create(&bochs_ops, mmap_base, mmap_len);
if (info == NULL) {
munmap(mmap_base, mmap_len);
return -ENOMEM;
}
return 0;
}
int hsmci_init (SIM_HBA *hba)
{
CONFIG_INFO *cfg;
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci = NULL;
uintptr_t base;
ext = (SIM_MMC_EXT *)hba->ext;
cfg = (CONFIG_INFO *)&hba->cfg;
hba->verbosity = 4;
if (!ext->opts) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: missing board-specific options\n");
goto ARGSERR;
}
if ((hsmci = calloc(1, sizeof(hsmci_ext_t))) == NULL) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: alloc memory failed\n");
goto ERR;
}
cfg->MemLength[0] = 0x1000;
cfg->NumMemWindows = 1;
cfg->MemBase[0] = cfg->IOPort_Base[0];
base = (uintptr_t)mmap_device_memory(NULL, cfg->MemLength[0],
PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, cfg->MemBase[0]);
if (base == (uintptr_t)MAP_FAILED) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_memory failed\n");
goto ERR;
}
hsmci->clock = 133000000;
hsmci->base = base;
hsmci->hba = hba;
ext->handle = hsmci;
ext->clock = hsmci->clock;
ext->detect = _hsmci_detect;
ext->powerup = _hsmci_powerup;
ext->powerdown = _hsmci_powerdown;
ext->cfg_bus = _hsmci_cfg_bus;
ext->set_clock = _hsmci_clock;
ext->set_blksz = _hsmci_block_size;
ext->interrupt = _hsmci_interrupt;
ext->command = _hsmci_command;
ext->setup_dma = _hsmci_setup_dma;
ext->dma_done = _hsmci_dma_done;
ext->setup_pio = _hsmci_setup_pio;
ext->pio_done = _hsmci_pio_done;
ext->shutdown = _hsmci_shutdown;
/* Parse options */
hsmci->port = -1;
hsmci->blksz = BLK_LENGTH;
hsmci->slot = 0;
/* Hardcode DMAC controller base address according to G45 datasheet
* since this driver is specifically for G45 SoC */
hsmci->dbase = DMAC_BASE;
if (!ext->opts)
goto ARGSERR;
if (hsmci_args(hba, ext->opts) == -1)
goto ARGSERR;
/*
* Set Src/Dst Request peripheral identifier SRC_PER/DST_PER
* handshaking interface # according to Table 41-1 DMA Channel Definition
* According to datasheet Table 35-2, the I/O line of mci0_da0 is pa2.
* According to datasheet Table 35-2, the I/O line of mci1_da0 is pa23.
*/
if (hsmci->port == 0) {
hsmci->dintf = 0;
hsmci->da0_mask = (1<<2);
} else {
hsmci->dintf=13;
hsmci->da0_mask = (1<<23);
}
/* Map G45 PIOA for polling busy signal */
pioa_pdsr = (uint32_t *)mmap_device_memory(NULL, 4,
PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, PIOA_PDSR);
if (pioa_pdsr == (uint32_t *)MAP_FAILED) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_memory failed\n");
goto ERR;
}
if ( (uintptr_t) MAP_FAILED == ( hsmci->pio_base = mmap_device_io( AT91SAM9G45_PIO_SIZE, AT91SAM9G45_PIOD_BASE ) ) ) {
slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_io for PIOD_PDSR failed" );
goto ERR;
}
/* Configure CD and WP PIO */
InterruptDisable();
#define CFG_PIO(reg) out32( hsmci->pio_base + (reg), AT91SAM9G45_MCI_PIO_BITS )
CFG_PIO( AT91SAM9G45_PIO_PER ); /* Ensable PIO */
CFG_PIO( AT91SAM9G45_PIO_ODR ); /* Disable output */
CFG_PIO( AT91SAM9G45_PIO_IFDR ); /* Disable glitch input filter */
CFG_PIO( AT91SAM9G45_PIO_CODR ); /* Clear output data */
CFG_PIO( AT91SAM9G45_PIO_IDR ); /* Disable interrupt */
CFG_PIO( AT91SAM9G45_PIO_MDDR ); /* Disable multi-driver */
CFG_PIO( AT91SAM9G45_PIO_PUER ); /* Enable pull-up */
CFG_PIO( AT91SAM9G45_PIO_OWDR ); /* Output write disable */
#undef CFG_PIO
InterruptEnable();
/* Configure capacity of controller */
ext->hccap |= MMC_HCCAP_BW1 | MMC_HCCAP_BW4 | MMC_HCCAP_DMA | MMC_HCCAP_BW8 | MMC_HCCAP_HS;
// Use the flag MMC_HCCAP_NOCD_BUSY to inform the MMCSD stack that this hardware has R1B bug
// ext->hccap |= MMC_HCCAP_BW1 | MMC_HCCAP_BW4 | MMC_HCCAP_DMA | MMC_HCCAP_BW8 | MMC_HCCAP_HS | MMC_HCCAP_NOCD_BUSY;
/* Disable the controller and soft reset */
WRITE32(MCI_CR, SWRST | PWSDIS);
delay (100);
WRITE32(MCI_CR, MCIDIS | PWSDIS);
/* Disable DMA */
WRITE32(MCI_DMA, (READ32(MCI_DMA) & (~(DMAEN))));
/* Enable the controller */
WRITE32(MCI_CR, MCIEN | PWSDIS);
WRITE32(MCI_IDR, 0xffffffff);
/* Set Timeout to Max */
WRITE32(MCI_DTOR, 0x7f);
/* Use the lowest baudrate */
WRITE32 (MCI_MR, 0xff | WRPROOF| RDPROOF);
hsmci->dmac_dev = dmac_init(hsmci);
if (hsmci->dmac_dev == NULL) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: dmafuncs init FAILED\n");
goto ERR;
}
hsmci->dmac_dev->io_addr = cfg->MemBase[0] + MCI_FIFO;
hsmci->dmac_dev->blksz = hsmci->blksz;
/* Select slot, set bus to 1 bit */
WRITE32 (MCI_SDCR, hsmci->slot);
if (!cfg->Description[0])
strncpy(cfg->Description, "Atmel HSMCI ", sizeof(cfg->Description));
if ( (uintptr_t) MAP_FAILED == ( hsmci->pmc_base = mmap_device_io(PMC_SIZE, PMC_BASE) ) ) {
slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_io for PMC failed" );
goto ERR;
}
return (MMC_SUCCESS);
ARGSERR:
printf("\nImproper board-specific options used. Accepting args: \n");
printf(" port=# The MCI port been used (0 or 1)\n");
printf("NOTE:\n");
printf(" 1. The args are seperated by colon ':'\n");
printf("Example:\n");
printf("at91sam9g45 port 0: devb-mmcsd-at91sam9g45 mmcsd ioport=0xFFF80000,irq=11,bs=port=0\n");
printf("at91sam9g45 port 1: devb-mmcsd-at91sam9g45 mmcsd ioport=0xFFFD0000,irq=29,bs=port=1\n");
ERR:
if (hsmci) {
munmap_device_memory ((void *)hsmci->base, (uint32_t)cfg->MemLength[0]);
if (hsmci->pio_base)
munmap_device_io (hsmci->pio_base, AT91SAM9G45_PIO_SIZE);
free (hsmci);
}
if (pioa_pdsr != (uint32_t *)MAP_FAILED)
munmap_device_memory ((void *)pioa_pdsr, 4);
return (MMC_FAILURE);
}
void can_dev_init(unsigned int base_address, unsigned int bit_speed,
unsigned char extended_frame)
{
BYTE ch;
#ifdef SSV_CAN
printf("Using SSV_CAN memory access\n");
BaseAddress = base_address;
#else
printf("Using ECAN527 memory access\n");
BaseAddress = (unsigned int) mmap_device_memory(NULL,
I82527_MAP_SIZE,
PROT_READ | PROT_WRITE | PROT_NOCACHE,
0, base_address);
#endif
Speed = bit_speed;
set_extended_frame = extended_frame;
//ThreadCtl(_NTO_TCTL_IO, NULL); /// this has already been done in can_man
#ifdef DO_TRACE
printf("BaseAddress 0x%02x, Speed %d, %s\n",
BaseAddress, Speed,
set_extended_frame?"extended frame":"standard frame");
fflush(stdout);
#endif
/* wait until Reset */
do
{
ch=Read_REG(CPU_IF_REG);
/* 0x1XXX XXXX-- CEn
|||| |||--- 0
|||| ||---- MUX
|||| |----- Sleep
||||------- PwD
|||-------- DMC
||--------- DSC
|---------- RstST = 0, normal operation */
}
while ((ch & 0x80) != 0x00);
#ifdef DO_TRACE
STATUS=Read_REG(STATUS_REG);
printf("can_dev_init: STATUS 0x%02x\n", STATUS);
#endif
Write_REG(CONTROL_REG,0x41);
/* 0x0100 0001 - Init (Software-) Enabled
|||--- IE Disabled
||---- SIE Disabled, no interrupt will be generated
| if a bus error
|----- EIE Disabled, no interrupt will be generated
if a change in error status */
//sleep(1);//for Busoff
#ifdef SSV_CAN
Write_REG(CPU_IF_REG,0x60);
/* 0x0110 0000 - CEn disabled, Clock out signal
|||| |||--- Reserved
|||| ||---- MUX, normal operation
|||| |----- Sleep ==>
||||------- PwD ==> both power down & sleep mode not active
|||-------- DMC, MCLK is equal to SCLK/2
||--------- DSC, SCLK is equal to XTAL/2
|---------- normal operation */
#else
Write_REG(CPU_IF_REG, 0);
#endif
#ifdef SSV_CAN
Write_REG(BUS_CON_REG,0x40);
#else
Write_REG(CLKOUT_REG, 0x0);
Write_REG(BUS_CON_REG,0x0);
#endif
/* 0x0100 0000 - DcR0, disconnect RX0 input Enabled
|||| |||--- DcR1, disconnect RX1 input Enabled
|||| ||---- A zero must always be written to this bit
|||| |----- DcT1, disconnect TX1 output driver Enabled
||||------- A zero must always be written to this bit
|||-------- POL
||--------- CoBy, normal operation, RX0-1 are the inputs to the
| input comparator
|---------- A zero must always be written to this bit */
Write_REG(STATUS_REG,0x00);
/* 0x0000 0000 - ==>
|||| |||--- LEC 0-2, No Error
|||| |----- TXOK, No messege succesfully transmitted
||||------- RXOK, No message succesfully received
|||-------- Wake, Wake Up interrupt is reset by reading status Reg.
||--------- Warn, there is no abnormal accurrence of errors
|---------- BOff, 82527 is not bus off */
Set_Bit_Speed(Speed);
/* Define alll MSG as invalid */
Write_REG(MSG_1+CTRL_0_REG,0x55);
Write_REG(MSG_2+CTRL_0_REG,0x55);
Write_REG(MSG_3+CTRL_0_REG,0x55);
Write_REG(MSG_4+CTRL_0_REG,0x55);
Write_REG(MSG_5+CTRL_0_REG,0x55);
Write_REG(MSG_6+CTRL_0_REG,0x55);
Write_REG(MSG_7+CTRL_0_REG,0x55);
Write_REG(MSG_8+CTRL_0_REG,0x55);
Write_REG(MSG_9+CTRL_0_REG,0x55);
Write_REG(MSG_10+CTRL_0_REG,0x55);
Write_REG(MSG_11+CTRL_0_REG,0x55);
Write_REG(MSG_12+CTRL_0_REG,0x55);
Write_REG(MSG_13+CTRL_0_REG,0x55);
Write_REG(MSG_14+CTRL_0_REG,0x55);
Write_REG(MSG_15+CTRL_0_REG,0x55);
/* don't apply global accepting filters*/
Write_REG(G_MASK_S_REG0,0xFF);
Write_REG(G_MASK_S_REG1,0xFF);
Write_REG(G_MASK_E_REG0,0xFF);
Write_REG(G_MASK_E_REG1,0xFF);
Write_REG(G_MASK_E_REG2,0xFF);
Write_REG(G_MASK_E_REG3,0xFF);
/* Receive ALL in Object 15 */
Write_REG(M_MASK_REG0,0x00);
Write_REG(M_MASK_REG1,0x00);
Write_REG(M_MASK_REG2,0x00);
Write_REG(M_MASK_REG3,0x00);
/* Reveive conf. */
Write_REG(MSG_15+CTRL_0_REG,0x99);
/* 0x1001 1001 - ==>
|||| |||--- ==> IntPnd, MSB=0 no interrupt was generated by message
|||| ||---- ==>
|||| |----- ==> RXIE, MSB=1 an interrupt will be generated by reception
||||------- ==>
|||-------- ==> TXIE, MSB=0 no interrupt will be generated by transmit
||--------- ==>
|---------- ==> MsgVal, MSB=1 message valid */
Write_REG(MSG_15+CTRL_1_REG,0x55);
/* 0x0101 0101 - ==>
|||| |||--- ==> NewDat, MSB=0 no new Data
|||| ||---- ==>
|||| |----- ==> MsgLst, MSB=0 no message was lost
||||------- ==>
|||-------- ==> TxRqst, MSB=0 no waiting for transmit
||--------- ==>
|---------- ==> RmtPnd, MSB=0 no waiting for remote request */
if(set_extended_frame)
Write_REG(MSG_15+0x06,0x84);
/* 0x1000 0100 - 0x84
|||| |||--- ==> Reserved
|||| ||---- ==> 1- extended identifier 29 / 0 - standard identifier 11-bit
|||| |----- ==> Dir, 0 direction receive
||||------- ==>
|||-------- ==>
||--------- ==>
|---------- ==> DLC, 8 Data Length Code */
else
Write_REG(MSG_15+0x06,0x80);
Write_REG(MSG_1+0x06,0x88);
/* 0x1000 1000 - 0x88
|||| |||--- ==> Reserved
|||| ||---- ==> standard identifier 11-bit
|||| |----- ==> Dir, 0 direction receive
||||------- ==>
|||-------- ==>
||--------- ==>
|---------- ==> DLC, 8 Data Length Code */
#undef DEBUG_SIE
#ifdef DEBUG_SIE
Write_REG(CONTROL_REG,0x4E); /* EIE, SIE,IE Enabled */
#else
Write_REG(CONTROL_REG,0x4A); /* EIE enabled, IE Enabled */
#endif
/* 0x0100 1010 - Init (Software-) disabled
|||--- IE enabled
||---- SIE enabled, an interrupt will be generated
| if a change in error status
|----- EIE enabled, an interrupt will be generated
if a bus error*/
}
/******************************
* DMAC functions START
*****************************/
static dmac_dev_t * dmac_init (hsmci_ext_t *hsmci)
{
rsrc_request_t req;
dmac_dev_t *dmac_dev;
int timeout;
/* Allocated memory for channel */
dmac_dev = (dmac_dev_t*)calloc(1, sizeof (dmac_dev_t));
if (dmac_dev == NULL) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: DMAC calloc failed\n");
return NULL;
}
/* Map DMAC controller */
dmac_dev->dmac = (at91sam9xx_dmac_t *)mmap_device_memory(NULL,0x200,
PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, (uint32_t)(hsmci->dbase));
if (dmac_dev->dmac == MAP_FAILED) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: DMAC MAP_FAILED\n");
free (dmac_dev);
return NULL;
}
/* Apply DMAC channel */
memset(&req, 0, sizeof(req));
req.length = 1;
req.flags = RSRCDBMGR_DMA_CHANNEL;
if (rsrcdbmgr_attach( &req, 1) == -1) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: Cannot acquire DMAC channel\n");
munmap_device_memory((void *)dmac_dev->dmac, sizeof(at91sam9xx_dmac_t));
free (dmac_dev);
return NULL;
} else {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: Use DMAC channel %lld\n", req.start);
dmac_dev->chid = req.start;
}
/* Stop channel in case it is running */
dmac_dev->dmac->chdr = 1 << (dmac_dev->chid);
timeout = 0;
while (dmac_dev->dmac->chsr & (1 <<dmac_dev->chid)) {
delay (1);
if (timeout++ > 2000) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "%s: release DMAC channel time out\n", __func__);
break;
}
}
/* Reset HW LLI table*/
memset(&(dmac_dev->dmac->lli[dmac_dev->chid]), 0, sizeof(at91sam9xx_dmac_lli_t));
/* Alloc buffer link list memory */
dmac_dev->lli = mmap (0, (MAX_LLI_NUM) * sizeof(at91sam9xx_dmac_bd_t),
PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, NOFD, 0);
if (dmac_dev->lli == MAP_FAILED) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: DMA setup_xfer map failed\n");
return NULL;
}
/* Initilize the link list */
memset(dmac_dev->lli, 0, MAX_LLI_NUM * sizeof(at91sam9xx_dmac_bd_t));
/* Get link list physical address here and assign them in setup_xfer to save CPU time */
lli_mphy = (uint32_t) mphys(&dmac_dev->lli[0]);
lli_size = sizeof(at91sam9xx_dmac_bd_t);
/*
* Associate Channel chid Src/Dst Request peripheral identifier
* SRC_PER/DST_PER handshaking interface
*/
dmac_dev->dmac->lli[dmac_dev->chid].cfg = DMAC_SOD_DISABLE
| (hsmci->dintf << 0) | (hsmci->dintf << 4);
dmac_dev->dmac->en = DMAC_ENABLE;
return dmac_dev;
}
struct ics660b *ics660_drv_init(int pci_ind)
{
int page;
long nchan=16,i;
long status;
long interp_val,channel;
double state_time = STATE_TIME;
double pi;
struct pci_base ics660pci;
uint32_t sequencer_base = 0x00100000;
uint32_t *mod_control_reg, *m2base;
uint32_t chip;
long wr_addr,bl_adv,seq_word;
int pci_max=3;
struct ics660b *ics660_struct;
volatile unsigned char *ics660_mem0;
volatile unsigned char *ics660_mem1;
struct ics660_registers ics660_regs;
struct dc60m_registers dc60m_regs;
struct timespec sl_time,hold_time;
ics660_struct = (struct ics660b *)calloc((size_t) 1,(size_t) sizeof(struct ics660b));
/* Initialize card to get base address */
if( get_pci_base_addr(DEVICE_ID,VENDOR_ID,pci_ind,&ics660pci) == -1 )
{
perror("***** FAILED TO GET BASE ADDRESSES *****\n");
fprintf(stderr,"error %d %d %d\n",DEVICE_ID,VENDOR_ID,pci_ind);
exit(0);
}
/* Memory map address space */
if( (ics660_mem0 = mmap_device_memory( 0, (size_t) ICS660_MEM_SIZE,
PROT_EXEC|PROT_READ|PROT_WRITE|PROT_NOCACHE,
0,(uint32_t) ics660pci.base0))
== MAP_FAILED)
{
perror("***** FAILED TO MEMORY MAP CARD MEMORY *****\n");
exit (0);
}
if( (ics660_mem1 = mmap_device_memory( 0, (size_t) ICS660_MEM_SIZE,
PROT_EXEC|PROT_READ|PROT_WRITE|PROT_NOCACHE,
0,(uint32_t) ics660pci.base1))
== MAP_FAILED)
{
perror("***** FAILED TO MEMORY MAP CARD MEMORY *****\n");
exit (0);
}
m2base = (uint32_t *)(ics660_mem0 + (uint32_t)M2BASE_OFFSET);
mod_control_reg = (uint32_t *)(ics660_mem0 + (uint32_t)M2BASE2_OFFSET);
assign_register_addresses(ics660_mem0,&ics660_regs,m2base,&dc60m_regs);
ics660_struct->mem0 = ics660_mem0;
ics660_struct->mem1 = ics660_mem1;
ics660_struct->pci_io = ics660pci.io_base;
ics660_struct->regs = ics660_regs;
ics660_struct->dc60m_regs = dc60m_regs;
ics660_struct->mod_control_reg = mod_control_reg;
/* Write to board reset register */
*(unsigned int*)(ics660_regs.board_reset) = RESET_VALUE;
*(unsigned int*)(ics660_regs.interrupt_mask) = (uint32_t)IMASK_VALUE;
/*** Select clock source (internal/external) (for some reason this is necessary) */
set_parameter(ics660_struct,CLOCK_SELECT,EXTERNAL);
return ics660_struct;
}
int _open_PLX9080(unsigned int *BASEA, unsigned int *BASEB, unsigned int *BASEB_phys, int *pci_handle, unsigned int *mmap_io_ptr, int *interrupt_line, int print){
volatile unsigned char *BASE0, *BASE1;
unsigned flags, lastbus, version, hardware, bus, device;
int temp;
unsigned pci_index=0;
struct _pci_config_regs pci_reg;
unsigned int *mmap_ptr;
/* CONNECT TO PCI SERVER */
*pci_handle=pci_attach(flags);
if (*pci_handle == -1){
perror("Cannot attach to PCI system");
return -1;
}
/* CHECK FOR PCI BUS */
temp=pci_present(&lastbus, &version, &hardware);
if(temp != PCI_SUCCESS){
perror("Cannot find PCI BIOS");
return -1;
}
/* FIND DEVICE */
temp=pci_find_device(DEVICE_ID, VENDOR_ID, pci_index, &bus, &device);
if(temp != PCI_SUCCESS){
perror("Cannot find GC314-PCI/FS Digital Receiver Card");
return -1;
}
/* READ THE DEVICE PCI CONFIGURATION */
temp=pci_read_config32(bus, device, 0, 16, (char *)&pci_reg);
if(temp != PCI_SUCCESS){
perror("Cannot read from configuration space of the GC314 PCI/FS digital receiver card");
return -1;
}
BASEIO=(int)pci_reg.Base_Address_Regs[1]-1;
/* ALLOW I/O ACCESS ON THIS THREAD */
temp=ThreadCtl(_NTO_TCTL_IO,0);
if (temp==-1){
perror("Unable to attach I/O privileges to thread");
return -1;
}
/* MAP THE IO SPACE TO BE ABLE TO R/W TO PCI IO */
mmap_ptr=(unsigned int *)mmap_device_io(256, pci_reg.Base_Address_Regs[2]-1);
if ((int)mmap_io_ptr == MAP_DEVICE_FAILED){
perror("Device I/O mapping failed");
return -1;
}
/* TRY TO MEMORY MAP TO THE DEVICE REGISTER SPACE */
BASE0=mmap_device_memory(0, 1048576, PROT_EXEC|PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, pci_reg.Base_Address_Regs[0]);
//BASE0=mmap_device_memory(0, 256, PROT_EXEC|PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, pci_reg.Base_Address_Regs[2]-1);
if ((BASE0 == MAP_FAILED) | (BASE1 == MAP_FAILED)){
perror("Device Memory mapping failed");
return -1;
}
/* TRY TO READ PCI DEVICE PARAMETERS */
pci_write_config16(bus, device, PLX9080_PCIICR, 1, &vPLX9080_PCIICR);
*((uint16*)(BASE0+PLX9080_BIGEND))=vPLX9080_BIGEND;
*((uint16*)(BASE0+PLX9080_BIGEND))=0;
*((uint32*)(BASE0+PLX9080_CNTRL))=vPLX9080_CNTRL;
/* PRINT PLX9080 PARAMETERS */
if (print == 1){
printf(" PCI DEVICE PARAMETERS:\n");
printf(" lastbus= %d\n", lastbus);
printf(" version= %d\n", version);
printf(" hardware= %d\n", hardware);
printf(" bus= %d\n", bus);
printf(" device= %d\n", device);
printf(" MEMORY ALLOCATION:\n");
printf(" MEM Base (pci config)= 0x%x\n", pci_reg.Base_Address_Regs[0]);
printf(" IO Base1 (card ctrl)= 0x%x\n", pci_reg.Base_Address_Regs[2]);
printf(" IO Base2= 0x%x\n", pci_reg.Base_Address_Regs[1]);
printf(" Mapped BASE0= 0x%x\n", BASE0);
printf(" Mapped BASE1= 0x%x\n", BASE1);
}
*mmap_io_ptr=mmap_ptr;
pci_read_config16(bus, device, 0x18, 1, &vPLX9080_PCIICR);
printf("PCR 0x18 is %x\n", vPLX9080_PCIICR);
printf("mmap_io_ptr is %x\n", *mmap_io_ptr);
*BASEA=(int)BASE0;
//*BASEB=(int)BASE1;
*BASEB=(unsigned int)pci_reg.Base_Address_Regs[1]-1;
//*BASEB=mmap_io_ptr-1;
*BASEB_phys=(unsigned int)pci_reg.Base_Address_Regs[0];
*interrupt_line=pci_reg.Interrupt_Line;
printf("BASE0 is %x\n", BASE0);
printf("memory base + 0x00 is %x\n", *(uint32*)(BASE0));
return 1;
}
