code *nteh_monitor_prolog(Symbol *shandle)
{
/*
* PUSH handle
* PUSH offset _d_monitor_handler
* PUSH FS:__except_list
* MOV FS:__except_list,ESP
* CALL _d_monitor_prolog
*/
CodeBuilder cdb1;
CodeBuilder cdb;
assert(config.exe == EX_WIN32); // BUG: figure out how to implement for other EX's
if (shandle->Sclass == SCfastpar)
{ assert(shandle->Spreg != DX);
assert(shandle->Spreg2 == NOREG);
cdb.gen1(0x50 + shandle->Spreg); // PUSH shandle
}
else
{
// PUSH shandle
useregs(mCX);
cdb.genc1(0x8B,modregrm(2,CX,4),FLconst,4 * (1 + needframe) + shandle->Soffset + localsize);
cdb.last()->Isib = modregrm(0,4,SP);
cdb.gen1(0x50 + CX); // PUSH ECX
}
Symbol *smh = getRtlsym(RTLSYM_MONITOR_HANDLER);
cdb.gencs(0x68,0,FLextern,smh); // PUSH offset _d_monitor_handler
makeitextern(smh);
code cs;
useregs(mDX);
cs.Iop = 0x8B;
cs.Irm = modregrm(0,DX,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = getRtlsym(RTLSYM_EXCEPT_LIST);
cs.IEVoffset1 = 0;
cdb1.gen(&cs); // MOV EDX,FS:__except_list
cdb.gen1(0x50 + DX); // PUSH EDX
Symbol *s = getRtlsym(RTLSYM_MONITOR_PROLOG);
regm_t desregs = ~s->Sregsaved & ALLREGS;
cdb.append(getregs(desregs));
cdb.gencs(0xE8,0,FLfunc,s); // CALL _d_monitor_prolog
cs.Iop = 0x89;
NEWREG(cs.Irm,SP);
cdb.gen(&cs); // MOV FS:__except_list,ESP
cdb1.append(cdb);
return cdb1.finish();
}
code *nteh_unwind(regm_t retregs,unsigned index)
{ code *c;
code cs;
code *cs1;
code *cs2;
regm_t desregs;
int reg;
int local_unwind;
// Shouldn't this always be CX?
#if SCPP
reg = AX;
#else
reg = CX;
#endif
#if MARS
local_unwind = RTLSYM_D_LOCAL_UNWIND2;
#else
local_unwind = RTLSYM_LOCAL_UNWIND2;
#endif
desregs = (~rtlsym[local_unwind]->Sregsaved & (ALLREGS)) | mask[reg];
gensaverestore(retregs & desregs,&cs1,&cs2);
c = getregs(desregs);
cs.Iop = 0x8D;
cs.Irm = modregrm(2,reg,BPRM);
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL1 = FLconst;
// EBP offset of __context.prev
cs.IEV1.Vint = nteh_EBPoffset_prev();
c = gen(c,&cs); // LEA ECX,contextsym
genc2(c,0x68,0,index); // PUSH index
gen1(c,0x50 + reg); // PUSH ECX
#if MARS
//gencs(c,0xB8+AX,0,FLextern,nteh_scopetable()); // MOV EAX,&scope_table
gencs(c,0x68,0,FLextern,nteh_scopetable()); // PUSH &scope_table
gencs(c,0xE8,0,FLfunc,rtlsym[local_unwind]); // CALL __d_local_unwind2()
genc2(c,0x81,modregrm(3,0,SP),12); // ADD ESP,12
#else
gencs(c,0xE8,0,FLfunc,rtlsym[local_unwind]); // CALL __local_unwind2()
genc2(c,0x81,modregrm(3,0,SP),8); // ADD ESP,8
#endif
c = cat4(cs1,c,cs2,NULL);
return c;
}
code *nteh_monitor_epilog(regm_t retregs)
{
/*
* CALL _d_monitor_epilog
* POP FS:__except_list
*/
assert(config.exe == EX_WIN32); // BUG: figure out how to implement for other EX's
Symbol *s = getRtlsym(RTLSYM_MONITOR_EPILOG);
//desregs = ~s->Sregsaved & ALLREGS;
regm_t desregs = 0;
code *cs1;
code *cs2;
gensaverestore(retregs& desregs,&cs1,&cs2);
CodeBuilder cdb(getregs(desregs));
cdb.gencs(0xE8,0,FLfunc,s); // CALL __d_monitor_epilog
CodeBuilder cdb1(cs1);
CodeBuilder cdb2(cs2);
cdb1.append(cdb, cdb2);
code cs;
cs.Iop = 0x8F;
cs.Irm = modregrm(0,0,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = getRtlsym(RTLSYM_EXCEPT_LIST);
cs.IEVoffset1 = 0;
cdb1.gen(&cs); // POP FS:__except_list
return cdb1.finish();
}
code *nteh_unwind(regm_t retregs,unsigned index)
{
code cs;
regm_t desregs;
int reg;
int local_unwind;
// Shouldn't this always be CX?
#if SCPP
reg = AX;
#else
reg = CX;
#endif
#if MARS
local_unwind = RTLSYM_D_LOCAL_UNWIND2;
#else
local_unwind = RTLSYM_LOCAL_UNWIND2;
#endif
desregs = (~getRtlsym(local_unwind)->Sregsaved & (ALLREGS)) | mask[reg];
code *cs1;
code *cs2;
gensaverestore(retregs & desregs,&cs1,&cs2);
CodeBuilder cdb(getregs(desregs));
cs.Iop = 0x8D;
cs.Irm = modregrm(2,reg,BPRM);
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL1 = FLconst;
// EBP offset of __context.prev
cs.IEV1.Vint = nteh_EBPoffset_prev();
cdb.gen(&cs); // LEA ECX,contextsym
cdb.genc2(0x68,0,index); // PUSH index
cdb.gen1(0x50 + reg); // PUSH ECX
#if MARS
//cdb.gencs(0xB8+AX,0,FLextern,nteh_scopetable()); // MOV EAX,&scope_table
cdb.gencs(0x68,0,FLextern,nteh_scopetable()); // PUSH &scope_table
cdb.gencs(0xE8,0,FLfunc,getRtlsym(local_unwind)); // CALL __d_local_unwind2()
cdb.append(cod3_stackadj(NULL, -12));
#else
cdb.gencs(0xE8,0,FLfunc,getRtlsym(local_unwind)); // CALL __local_unwind2()
cdb.append(cod3_stackadj(NULL, -8));
#endif
CodeBuilder cdb1(cs1);
CodeBuilder cdb2(cs2);
cdb1.append(cdb, cdb2);
return cdb1.finish();
}
code *nteh_setsp(int op)
{ code cs;
cs.Iop = op;
cs.Irm = modregrm(2,SP,BPRM);
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL1 = FLconst;
// EBP offset of __context.esp
cs.IEV1.Vint = nteh_EBPoffset_esp();
return gen(CNIL,&cs); // MOV ESP,__context[EBP].esp
}
code *linux_unwind(regm_t retregs,unsigned index)
{ code *c;
code *cs1;
code *cs2;
int i;
regm_t desregs;
int reg;
int local_unwind;
// Shouldn't this always be CX?
#if SCPP
reg = AX;
#else
reg = CX;
#endif
#if MARS
local_unwind = RTLSYM_D_LOCAL_UNWIND2;
#else
local_unwind = RTLSYM_LOCAL_UNWIND2;
#endif
desregs = (~rtlsym[local_unwind]->Sregsaved & (ALLREGS)) | mask[reg];
gensaverestore(retregs & desregs,&cs1,&cs2);
c = getregs(desregs);
c = genc2(c,0x68,0,index); // PUSH index
#if MARS
// gencs(c,0x68,0,FLextern,nteh_scopetable()); // PUSH &scope_table
gencs(c,0xE8,0,FLfunc,rtlsym[local_unwind]); // CALL __d_local_unwind2()
genc2(c,0x81,modregrm(3,0,SP),4); // ADD ESP,12
#else
gencs(c,0xE8,0,FLfunc,rtlsym[local_unwind]); // CALL __local_unwind2()
genc2(c,0x81,modregrm(3,0,SP),8); // ADD ESP,8
#endif
c = cat4(cs1,c,cs2,NULL);
return c;
}
code *nteh_filter(block *b)
{
code cs;
CodeBuilder cdb;
assert(b->BC == BC_filter);
if (b->Bflags & BFLehcode) // if referenced __ecode
{
/* Generate:
mov EAX,__context[EBP].info
mov EAX,[EAX]
mov EAX,[EAX]
mov __ecode[EBP],EAX
*/
cdb.append(getregs(mAX));
cs.Iop = 0x8B;
cs.Irm = modregrm(2,AX,BPRM);
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL1 = FLconst;
// EBP offset of __context.info
cs.IEV1.Vint = nteh_EBPoffset_info();
cdb.gen(&cs); // MOV EAX,__context[EBP].info
cs.Irm = modregrm(0,AX,0);
cdb.gen(&cs); // MOV EAX,[EAX]
cdb.gen(&cs); // MOV EAX,[EAX]
cs.Iop = 0x89;
cs.Irm = modregrm(2,AX,BPRM);
cs.IFL1 = FLauto;
cs.IEVsym1 = nteh_ecodesym();
cs.IEVoffset1 = 0;
cdb.gen(&cs); // MOV __ecode[EBP],EAX
}
return cdb.finish();
}
code *nteh_epilog()
{
if (config.exe != EX_WIN32)
return NULL;
/* Generate:
mov ECX,__context[EBP].prev
mov FS:__except_list,ECX
*/
code cs;
CodeBuilder cdb;
unsigned reg;
#if MARS
reg = CX;
#else
reg = (tybasic(funcsym_p->Stype->Tnext->Tty) == TYvoid) ? AX : CX;
#endif
useregs(mask[reg]);
cs.Iop = 0x8B;
cs.Irm = modregrm(2,reg,BPRM);
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL1 = FLconst;
// EBP offset of __context.prev
cs.IEV1.Vint = nteh_EBPoffset_prev();
cdb.gen(&cs);
cs.Iop = 0x89;
cs.Irm = modregrm(0,reg,BPRM);
cs.Iflags |= CFfs;
cs.IFL1 = FLextern;
cs.IEVsym1 = getRtlsym(RTLSYM_EXCEPT_LIST);
cs.IEVoffset1 = 0;
cdb.gen(&cs);
return cdb.finish();
}
code *nteh_setsp(int op)
{
code cs;
cs.Iop = op;
cs.Irm = modregrm(2,SP,BPRM);
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL1 = FLconst;
// EBP offset of __context.esp
cs.IEV1.Vint = nteh_EBPoffset_esp();
CodeBuilder cdb;
cdb.gen(&cs); // MOV ESP,__context[EBP].esp
return cdb.finish();
}
code *nteh_epilog()
{
if (!(config.flags2 & CFG2seh))
return NULL;
/* Generate:
mov ECX,__context[EBP].prev
mov FS:__except_list,ECX
*/
code cs;
code *c;
unsigned reg;
#if MARS
reg = CX;
#else
reg = (tybasic(funcsym_p->Stype->Tnext->Tty) == TYvoid) ? AX : CX;
#endif
useregs(mask[reg]);
cs.Iop = 0x8B;
cs.Irm = modregrm(2,reg,BPRM);
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL1 = FLconst;
// EBP offset of __context.prev
cs.IEV1.Vint = nteh_EBPoffset_prev();
c = gen(CNIL,&cs);
cs.Iop = 0x89;
cs.Irm = modregrm(0,reg,BPRM);
cs.Iflags |= CFfs;
cs.IFL1 = FLextern;
cs.IEVsym1 = rtlsym[RTLSYM_EXCEPT_LIST];
cs.IEVoffset1 = 0;
return gen(c,&cs);
}
code *nteh_gensindex(int sindex)
{ code *c;
if (!(config.flags2 & CFG2seh))
return NULL;
// Generate:
// MOV -4[EBP],sindex
c = genc(NULL,0xC7,modregrm(1,0,BP),FLconst,(targ_uns)nteh_EBPoffset_sindex(),FLconst,sindex); // 7 bytes long
c->Iflags |= CFvolatile;
#ifdef DEBUG
//assert(GENSINDEXSIZE == calccodsize(c));
#endif
return c;
}
code *nteh_gensindex(int sindex)
{
if (config.exe != EX_WIN32)
return NULL;
// Generate:
// MOV -4[EBP],sindex
CodeBuilder cdb;
cdb.genc(0xC7,modregrm(1,0,BP),FLconst,(targ_uns)nteh_EBPoffset_sindex(),FLconst,sindex); // 7 bytes long
code *c = cdb.finish();
c->Iflags |= CFvolatile;
#ifdef DEBUG
//assert(GENSINDEXSIZE == calccodsize(c));
#endif
return c;
}
code *nteh_monitor_epilog(regm_t retregs)
{
/*
* CALL _d_monitor_epilog
* POP FS:__except_list
*/
code cs;
code *c;
code *cs1;
code *cs2;
code *cpop;
regm_t desregs;
Symbol *s;
assert(config.flags2 & CFG2seh); // BUG: figure out how to implement for other EX's
s = rtlsym[RTLSYM_MONITOR_EPILOG];
//desregs = ~s->Sregsaved & ALLREGS;
desregs = 0;
gensaverestore(retregs & desregs,&cs1,&cs2);
c = getregs(desregs);
c = gencs(c,0xE8,0,FLfunc,s); // CALL __d_monitor_epilog
cs.Iop = 0x8F;
cs.Irm = modregrm(0,0,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = rtlsym[RTLSYM_EXCEPT_LIST];
cs.IEVoffset1 = 0;
cpop = gen(NULL,&cs); // POP FS:__except_list
c = cat4(cs1,c,cs2,cpop);
return c;
}
code *nteh_monitor_prolog(Symbol *shandle)
{
/*
* PUSH handle
* PUSH offset _d_monitor_handler
* PUSH FS:__except_list
* MOV FS:__except_list,ESP
* CALL _d_monitor_prolog
*/
code *c1 = NULL;
code *c;
code cs;
Symbol *s;
regm_t desregs;
assert(config.flags2 & CFG2seh); // BUG: figure out how to implement for other EX's
if (shandle->Sclass == SCfastpar)
{ assert(shandle->Spreg != DX);
c = gen1(NULL,0x50 + shandle->Spreg); // PUSH shandle
}
else
{
// PUSH shandle
#if 0
c = genc1(NULL,0xFF,modregrm(2,6,4),FLconst,4 * (1 + needframe) + shandle->Soffset + localsize);
c->Isib = modregrm(0,4,SP);
#else
useregs(mCX);
c = genc1(NULL,0x8B,modregrm(2,CX,4),FLconst,4 * (1 + needframe) + shandle->Soffset + localsize);
c->Isib = modregrm(0,4,SP);
gen1(c,0x50 + CX); // PUSH ECX
#endif
}
s = rtlsym[RTLSYM_MONITOR_HANDLER];
c = gencs(c,0x68,0,FLextern,s); // PUSH offset _d_monitor_handler
makeitextern(s);
#if 0
cs.Iop = 0xFF;
cs.Irm = modregrm(0,6,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = rtlsym[RTLSYM_EXCEPT_LIST];
cs.IEVoffset1 = 0;
gen(c,&cs); // PUSH FS:__except_list
#else
useregs(mDX);
cs.Iop = 0x8B;
cs.Irm = modregrm(0,DX,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = rtlsym[RTLSYM_EXCEPT_LIST];
cs.IEVoffset1 = 0;
c1 = gen(c1,&cs); // MOV EDX,FS:__except_list
gen1(c,0x50 + DX); // PUSH EDX
#endif
s = rtlsym[RTLSYM_MONITOR_PROLOG];
desregs = ~s->Sregsaved & ALLREGS;
c = cat(c,getregs(desregs));
c = gencs(c,0xE8,0,FLfunc,s); // CALL _d_monitor_prolog
cs.Iop = 0x89;
NEWREG(cs.Irm,SP);
gen(c,&cs); // MOV FS:__except_list,ESP
return cat(c1,c);
}
code *cdvector(elem *e, regm_t *pretregs)
{
/* e should look like one of:
* vector
* |
* param
* / \
* param op2
* / \
* op op1
*/
if (!config.fpxmmregs)
{ printf("SIMD operations not supported on this platform\n");
exit(1);
}
unsigned n = el_nparams(e->E1);
elem **params = (elem **)malloc(n * sizeof(elem *));
assert(params);
elem **tmp = params;
el_paramArray(&tmp, e->E1);
#if 0
printf("cdvector()\n");
for (int i = 0; i < n; i++)
{
printf("[%d]: ", i);
elem_print(params[i]);
}
#endif
if (*pretregs == 0)
{ /* Evaluate for side effects only
*/
CodeBuilder cdb;
for (int i = 0; i < n; i++)
{
cdb.append(codelem(params[i], pretregs, FALSE));
*pretregs = 0; // in case they got set
}
return cdb.finish();
}
assert(n >= 2 && n <= 4);
elem *eop = params[0];
elem *op1 = params[1];
elem *op2 = NULL;
tym_t ty2 = 0;
if (n >= 3)
{ op2 = params[2];
ty2 = tybasic(op2->Ety);
}
unsigned op = el_tolong(eop);
#ifdef DEBUG
assert(!isXMMstore(op));
#endif
tym_t ty1 = tybasic(op1->Ety);
unsigned sz1 = _tysize[ty1];
// assert(sz1 == 16); // float or double
regm_t retregs;
CodeBuilder cdb;
if (n == 3 && ty2 == TYuchar && op2->Eoper == OPconst)
{ // Handle: op xmm,imm8
retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
cdb.append(codelem(op1,&retregs,FALSE)); // eval left leaf
unsigned reg = findreg(retregs);
int r;
switch (op)
{
case PSLLD: r = 6; op = 0x660F72; break;
case PSLLQ: r = 6; op = 0x660F73; break;
case PSLLW: r = 6; op = 0x660F71; break;
case PSRAD: r = 4; op = 0x660F72; break;
case PSRAW: r = 4; op = 0x660F71; break;
case PSRLD: r = 2; op = 0x660F72; break;
case PSRLQ: r = 2; op = 0x660F73; break;
case PSRLW: r = 2; op = 0x660F71; break;
case PSRLDQ: r = 3; op = 0x660F73; break;
case PSLLDQ: r = 7; op = 0x660F73; break;
default:
printf("op = x%x\n", op);
assert(0);
break;
}
cdb.append(getregs(retregs));
cdb.genc2(op,modregrmx(3,r,reg-XMM0), el_tolong(op2));
}
else if (n == 2)
{ /* Handle: op xmm,mem
* where xmm is written only, not read
*/
code cs;
if ((op1->Eoper == OPind && !op1->Ecount) || op1->Eoper == OPvar)
{
cdb.append(getlvalue(&cs, op1, RMload)); // get addressing mode
}
else
{
regm_t rretregs = XMMREGS;
cdb.append(codelem(op1, &rretregs, FALSE));
unsigned rreg = findreg(rretregs) - XMM0;
cs.Irm = modregrm(3,0,rreg & 7);
cs.Iflags = 0;
cs.Irex = 0;
if (rreg & 8)
cs.Irex |= REX_B;
}
retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
unsigned reg;
cdb.append(allocreg(&retregs, ®, e->Ety));
code_newreg(&cs, reg - XMM0);
cs.Iop = op;
cdb.gen(&cs);
}
else if (n == 3 || n == 4)
{ /* Handle:
* op xmm,mem // n = 3
* op xmm,mem,imm8 // n = 4
* Both xmm and mem are operands, evaluate xmm first.
*/
code cs;
retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
cdb.append(codelem(op1,&retregs,FALSE)); // eval left leaf
unsigned reg = findreg(retregs);
if ((op2->Eoper == OPind && !op2->Ecount) || op2->Eoper == OPvar)
{
cdb.append(getlvalue(&cs, op2, RMload | retregs)); // get addressing mode
}
else
{
unsigned rretregs = XMMREGS & ~retregs;
cdb.append(scodelem(op2, &rretregs, retregs, TRUE));
unsigned rreg = findreg(rretregs) - XMM0;
cs.Irm = modregrm(3,0,rreg & 7);
cs.Iflags = 0;
cs.Irex = 0;
if (rreg & 8)
cs.Irex |= REX_B;
}
cdb.append(getregs(retregs));
if (n == 4)
{
switch (op)
{
case CMPPD: case CMPSS: case CMPSD: case CMPPS:
case PSHUFD: case PSHUFHW: case PSHUFLW:
case BLENDPD: case BLENDPS: case DPPD: case DPPS:
case MPSADBW: case PBLENDW:
case ROUNDPD: case ROUNDPS: case ROUNDSD: case ROUNDSS:
case SHUFPD: case SHUFPS:
break;
default:
printf("op = x%x\n", op);
assert(0);
break;
}
elem *imm8 = params[3];
cs.IFL2 = FLconst;
cs.IEV2.Vsize_t = el_tolong(imm8);
}
code_newreg(&cs, reg - XMM0);
cs.Iop = op;
cdb.gen(&cs);
}
else
assert(0);
cdb.append(fixresult(e,retregs,pretregs));
free(params);
freenode(e);
return cdb.finish();
}
code *xmmeq(elem *e, unsigned op, elem *e1, elem *e2,regm_t *pretregs)
{
tym_t tymll;
unsigned reg;
int i;
code cs;
elem *e11;
bool regvar; /* TRUE means evaluate into register variable */
regm_t varregm;
unsigned varreg;
targ_int postinc;
//printf("xmmeq(e1 = %p, e2 = %p, *pretregs = %s)\n", e1, e2, regm_str(*pretregs));
int e2oper = e2->Eoper;
tym_t tyml = tybasic(e1->Ety); /* type of lvalue */
regm_t retregs = *pretregs;
if (!(retregs & XMMREGS))
retregs = XMMREGS; // pick any XMM reg
bool aligned = xmmIsAligned(e1);
cs.Iop = (op == OPeq) ? xmmstore(tyml, aligned) : op;
regvar = FALSE;
varregm = 0;
if (config.flags4 & CFG4optimized)
{
// Be careful of cases like (x = x+x+x). We cannot evaluate in
// x if x is in a register.
if (isregvar(e1,&varregm,&varreg) && // if lvalue is register variable
doinreg(e1->EV.sp.Vsym,e2) && // and we can compute directly into it
varregm & XMMREGS
)
{ regvar = TRUE;
retregs = varregm;
reg = varreg; /* evaluate directly in target register */
}
}
if (*pretregs & mPSW && !EOP(e1)) // if evaluating e1 couldn't change flags
{ // Be careful that this lines up with jmpopcode()
retregs |= mPSW;
*pretregs &= ~mPSW;
}
CodeBuilder cdb;
cdb.append(scodelem(e2,&retregs,0,TRUE)); // get rvalue
// Look for special case of (*p++ = ...), where p is a register variable
if (e1->Eoper == OPind &&
((e11 = e1->E1)->Eoper == OPpostinc || e11->Eoper == OPpostdec) &&
e11->E1->Eoper == OPvar &&
e11->E1->EV.sp.Vsym->Sfl == FLreg
)
{
postinc = e11->E2->EV.Vint;
if (e11->Eoper == OPpostdec)
postinc = -postinc;
cdb.append(getlvalue(&cs,e11,RMstore | retregs));
freenode(e11->E2);
}
else
{ postinc = 0;
cdb.append(getlvalue(&cs,e1,RMstore | retregs)); // get lvalue (cl == CNIL if regvar)
}
cdb.append(getregs_imm(regvar ? varregm : 0));
reg = findreg(retregs & XMMREGS);
cs.Irm |= modregrm(0,(reg - XMM0) & 7,0);
if ((reg - XMM0) & 8)
cs.Irex |= REX_R;
// Do not generate mov from register onto itself
if (!(regvar && reg == XMM0 + ((cs.Irm & 7) | (cs.Irex & REX_B ? 8 : 0))))
{
cdb.gen(&cs); // MOV EA+offset,reg
if (op == OPeq)
checkSetVex(cdb.last(), tyml);
}
if (e1->Ecount || // if lvalue is a CSE or
regvar) // rvalue can't be a CSE
{
cdb.append(getregs_imm(retregs)); // necessary if both lvalue and
// rvalue are CSEs (since a reg
// can hold only one e at a time)
cssave(e1,retregs,EOP(e1)); // if lvalue is a CSE
}
cdb.append(fixresult(e,retregs,pretregs));
Lp:
if (postinc)
{
int reg = findreg(idxregm(&cs));
if (*pretregs & mPSW)
{ // Use LEA to avoid touching the flags
unsigned rm = cs.Irm & 7;
if (cs.Irex & REX_B)
rm |= 8;
cdb.genc1(0x8D,buildModregrm(2,reg,rm),FLconst,postinc);
if (tysize(e11->E1->Ety) == 8)
code_orrex(cdb.last(), REX_W);
}
else if (I64)
{
cdb.genc2(0x81,modregrmx(3,0,reg),postinc);
if (tysize(e11->E1->Ety) == 8)
code_orrex(cdb.last(), REX_W);
}
else
{
if (postinc == 1)
cdb.gen1(0x40 + reg); // INC reg
else if (postinc == -(targ_int)1)
cdb.gen1(0x48 + reg); // DEC reg
else
{
cdb.genc2(0x81,modregrm(3,0,reg),postinc);
}
}
}
freenode(e1);
return cdb.finish();
}
code *nteh_prolog()
{
code cs;
if (usednteh & NTEHpassthru)
{
/* An sindex value of -2 is a magic value that tells the
* stack unwinder to skip this frame.
*/
assert(config.exe & (EX_LINUX | EX_LINUX64 | EX_OSX | EX_OSX64 | EX_FREEBSD | EX_FREEBSD64 | EX_SOLARIS | EX_SOLARIS64 | EX_OPENBSD | EX_OPENBSD64));
cs.Iop = 0x68;
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vint = -2;
return gen(CNIL,&cs); // PUSH -2
}
/* Generate instance of struct __nt_context on stack frame:
[ ] // previous ebp already there
push -1 // sindex
mov EDX,FS:__except_list
push offset FLAT:scope_table // stable (not for MARS or C++)
push offset FLAT:__except_handler3 // handler
push EDX // prev
mov FS:__except_list,ESP
sub ESP,8 // info, esp for __except support
*/
// useregs(mAX); // What is this for?
CodeBuilder cdb1;
cs.Iop = 0x68;
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vint = -1;
cdb1.gen(&cs); // PUSH -1
if (MARS || (usednteh & NTEHcpp))
{
// PUSH &framehandler
cs.IFL2 = FLframehandler;
#if MARS
nteh_scopetable();
#endif
}
else
{
// Do stable
cs.Iflags |= CFoff;
cs.IFL2 = FLextern;
cs.IEVsym2 = nteh_scopetable();
cs.IEVoffset2 = 0;
cdb1.gen(&cs); // PUSH &scope_table
cs.IFL2 = FLextern;
cs.IEVsym2 = getRtlsym(RTLSYM_EXCEPT_HANDLER3);
makeitextern(getRtlsym(RTLSYM_EXCEPT_HANDLER3));
}
CodeBuilder cdb2;
cdb2.gen(&cs); // PUSH &__except_handler3
if (config.exe == EX_WIN32)
{
makeitextern(getRtlsym(RTLSYM_EXCEPT_LIST));
#if 0
cs.Iop = 0xFF;
cs.Irm = modregrm(0,6,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = getRtlsym(RTLSYM_EXCEPT_LIST);
cs.IEVoffset1 = 0;
cdb2.gen(&cs); // PUSH FS:__except_list
#else
useregs(mDX);
cs.Iop = 0x8B;
cs.Irm = modregrm(0,DX,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = getRtlsym(RTLSYM_EXCEPT_LIST);
cs.IEVoffset1 = 0;
cdb1.gen(&cs); // MOV EDX,FS:__except_list
cdb2.gen1(0x50 + DX); // PUSH EDX
#endif
cs.Iop = 0x89;
NEWREG(cs.Irm,SP);
cdb2.gen(&cs); // MOV FS:__except_list,ESP
}
CodeBuilder cdb3(cod3_stackadj(NULL, 8));
cdb1.append(cdb2, cdb3);
return cdb1.finish();
}
code *cdsetjmp(elem *e,regm_t *pretregs)
{ code cs;
code *c;
regm_t retregs;
unsigned stackpushsave;
unsigned flag;
c = NULL;
stackpushsave = stackpush;
#if SCPP
if (CPP && (funcsym_p->Sfunc->Fflags3 & Fcppeh || usednteh & NTEHcpp))
{
/* If in C++ try block
If the frame that is calling setjmp has a try,catch block then
the call to setjmp3 is as follows:
__setjmp3(environment,3,__cpp_longjmp_unwind,trylevel,funcdata);
__cpp_longjmp_unwind is a routine in the RTL. This is a
stdcall routine that will deal with unwinding for CPP Frames.
trylevel is the value that gets incremented at each catch,
constructor invocation.
funcdata is the same value that you put into EAX prior to
cppframehandler getting called.
*/
symbol *s;
s = except_gensym();
if (!s)
goto L1;
c = gencs(c,0x68,0,FLextern,s); // PUSH &scope_table
stackpush += 4;
genadjesp(c,4);
c = genc1(c,0xFF,modregrm(1,6,BP),FLconst,(targ_uns)-4);
// PUSH trylevel
stackpush += 4;
genadjesp(c,4);
cs.Iop = 0x68;
cs.Iflags = CFoff;
cs.Irex = 0;
cs.IFL2 = FLextern;
cs.IEVsym2 = rtlsym[RTLSYM_CPP_LONGJMP];
cs.IEVoffset2 = 0;
c = gen(c,&cs); // PUSH &_cpp_longjmp_unwind
stackpush += 4;
genadjesp(c,4);
flag = 3;
}
else
#endif
if (funcsym_p->Sfunc->Fflags3 & Fnteh)
{
/* If in NT SEH try block
If the frame that is calling setjmp has a try, except block
then the call to setjmp3 is as follows:
__setjmp3(environment,2,__seh_longjmp_unwind,trylevel);
__seth_longjmp_unwind is supplied by the RTL and is a stdcall
function. It is the name that MSOFT uses, we should
probably use the same one.
trylevel is the value that you increment at each try and
decrement at the close of the try. This corresponds to the
index field of the ehrec.
*/
int sindex_off;
sindex_off = 20; // offset of __context.sindex
cs.Iop = 0xFF;
cs.Irm = modregrm(2,6,BPRM);
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL1 = FLbprel;
cs.IEVsym1 = nteh_contextsym();
cs.IEVoffset1 = sindex_off;
c = gen(c,&cs); // PUSH scope_index
stackpush += 4;
genadjesp(c,4);
cs.Iop = 0x68;
cs.Iflags = CFoff;
cs.Irex = 0;
cs.IFL2 = FLextern;
cs.IEVsym2 = rtlsym[RTLSYM_LONGJMP];
cs.IEVoffset2 = 0;
c = gen(c,&cs); // PUSH &_seh_longjmp_unwind
stackpush += 4;
genadjesp(c,4);
flag = 2;
}
else
{
/* If the frame calling setjmp has neither a try..except, nor a
try..catch, then call setjmp3 as follows:
_setjmp3(environment,0)
*/
L1:
flag = 0;
}
cs.Iop = 0x68;
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vint = flag;
c = gen(c,&cs); // PUSH flag
stackpush += 4;
genadjesp(c,4);
c = cat(c,params(e->E1,REGSIZE));
c = cat(c,getregs(~rtlsym[RTLSYM_SETJMP3]->Sregsaved & (ALLREGS | mES)));
gencs(c,0xE8,0,FLfunc,rtlsym[RTLSYM_SETJMP3]); // CALL __setjmp3
c = genc2(c,0x81,modregrm(3,0,SP),stackpush - stackpushsave); // ADD ESP,8
genadjesp(c,-(stackpush - stackpushsave));
stackpush = stackpushsave;
retregs = regmask(e->Ety, TYnfunc);
return cat(c,fixresult(e,retregs,pretregs));
}
/***************
* Generate code for OPvecfill (broadcast).
* OPvecfill takes the single value in e1 and
* fills the vector type with it.
*/
code *cdvecfill(elem *e, regm_t *pretregs)
{
//printf("cdvecfill(e = %p, *pretregs = %s)\n",e,regm_str(*pretregs));
regm_t retregs = *pretregs & XMMREGS;
if (!retregs)
retregs = XMMREGS;
CodeBuilder cdb;
code *c;
code cs;
elem *e1 = e->E1;
#if 0
if ((e1->Eoper == OPind && !e1->Ecount) || e1->Eoper == OPvar)
{
cr = getlvalue(&cs, e1, RMload | retregs); // get addressing mode
}
else
{
unsigned rretregs = XMMREGS & ~retregs;
cr = scodelem(op2, &rretregs, retregs, TRUE);
unsigned rreg = findreg(rretregs) - XMM0;
cs.Irm = modregrm(3,0,rreg & 7);
cs.Iflags = 0;
cs.Irex = 0;
if (rreg & 8)
cs.Irex |= REX_B;
}
#endif
unsigned reg;
unsigned rreg;
unsigned varreg;
regm_t varregm;
tym_t ty = tybasic(e->Ety);
switch (ty)
{
case TYfloat4:
case TYfloat8:
if (config.avx &&
((e1->Eoper == OPind && !e1->Ecount) || e1->Eoper == OPvar && !isregvar(e1,&varregm,&varreg)) ||
tysize(ty) == 32 && !isregvar(e1,&varregm,&varreg)
)
{
Lint:
if (e1->Eoper == OPvar)
e1->EV.sp.Vsym->Sflags &= ~GTregcand;
// VBROADCASTSS XMM,MEM
cdb.append(getlvalue(&cs, e1, 0)); // get addressing mode
assert((cs.Irm & 0xC0) != 0xC0); // AVX1 doesn't have register source operands
cdb.append(allocreg(&retregs,®,ty));
cs.Iop = VBROADCASTSS;
cs.Irex &= ~REX_W;
code_newreg(&cs,reg - XMM0);
checkSetVex(&cs,ty);
cdb.gen(&cs);
}
else
{
// SHUFPS XMM0,XMM0,0 0F C6 /r ib
c = codelem(e1,&retregs,FALSE); // eval left leaf
cdb.append(c);
reg = findreg(retregs) - XMM0;
cdb.append(getregs(retregs));
cs.Iop = SHUFPS;
cs.Irm = modregxrmx(3,reg,reg);
cs.Iflags = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vsize_t = 0;
if (config.avx >= 2 || tysize(ty) == 32)
{
// VBROADCASTSS XMM,XMM
cs.Iop = VBROADCASTSS;
checkSetVex(&cs, ty);
}
cdb.gen(&cs);
}
break;
case TYdouble2:
case TYdouble4:
if (config.avx &&
((e1->Eoper == OPind && !e1->Ecount) || e1->Eoper == OPvar && !isregvar(e1,&varregm,&varreg)) ||
tysize(ty) == 32 && !isregvar(e1,&varregm,&varreg)
)
{
if (e1->Eoper == OPvar)
e1->EV.sp.Vsym->Sflags &= ~GTregcand;
// VBROADCASTSD XMM,MEM
cdb.append(getlvalue(&cs, e1, 0)); // get addressing mode
assert((cs.Irm & 0xC0) != 0xC0); // AVX1 doesn't have register source operands
cdb.append(allocreg(&retregs,®,ty));
cs.Iop = VBROADCASTSD;
cs.Irex &= ~REX_W;
code_newreg(&cs,reg - XMM0);
checkSetVex(&cs,ty);
cdb.gen(&cs);
}
else
{
// UNPCKLPD XMM0,XMM0 66 0F 14 /r
c = codelem(e1,&retregs,FALSE); // eval left leaf
cdb.append(c);
reg = findreg(retregs) - XMM0;
cdb.append(getregs(retregs));
cs.Iop = UNPCKLPD;
cs.Irm = modregxrmx(3,reg,reg);
cs.Iflags = 0;
if (config.avx >= 2 || tysize(ty) == 32)
{
// VBROADCASTSD XMM,XMM
cs.Iop = VBROADCASTSD;
checkSetVex(&cs, ty);
}
cdb.gen(&cs);
}
break;
case TYschar16:
case TYuchar16:
case TYschar32:
case TYuchar32:
{
/* MOVD XMM0,r
* PUNPCKLBW XMM0,XMM0
* PUNPCKLWD XMM0,XMM0
* PSHUFD XMM0,XMM0,0
*/
regm_t regm = ALLREGS;
c = codelem(e1,®m,FALSE); // eval left leaf
cdb.append(c);
unsigned r = findreg(regm);
c = allocreg(&retregs,®, e->Ety);
cdb.append(c);
reg -= XMM0;
cdb.gen2(LODD,modregxrmx(3,reg,r)); // MOVD reg,r
checkSetVex(cdb.last(),TYschar16);
cs.Iop = PUNPCKLBW;
cs.Irm = modregxrmx(3,reg,reg);
cs.Iflags = 0;
cdb.gen(&cs);
cs.Iop = PUNPCKLWD;
cdb.gen(&cs);
cs.Iop = PSHUFD;
cs.IFL2 = FLconst;
cs.IEV2.Vsize_t = 0;
checkSetVex(&cs,TYschar16);
cdb.gen(&cs);
if (tysize(ty) == 32)
{
// VINSERTF128 YMM0,YMM0,XMM0,1
cs.Iop = VINSERTF128;
cs.Irm = modregxrmx(3,reg,reg);
cs.Iflags = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vsize_t = 1;
checkSetVex(&cs,ty);
cdb.gen(&cs);
}
break;
}
case TYshort8:
case TYushort8:
case TYshort16:
case TYushort16:
{
regm_t regm = ALLREGS;
c = codelem(e1,®m,FALSE); // eval left leaf
cdb.append(c);
unsigned r = findreg(regm);
if (config.avx || tysize(ty) == 32)
{
/*
* VPXOR XMM0,XMM0,XMM0
* VPINSRW XMM0,XMM0,r,0
* VPINSRW XMM0,XMM0,r,1
* VPINSRW XMM0,XMM0,r,2
* VPINSRW XMM0,XMM0,r,3
*/
cdb.append(allocreg(&retregs,®, ty));
cdb.gen2(PXOR,modregxrmx(3,reg-XMM0,reg-XMM0));
checkSetVex(cdb.last(), TYshort8);
for (int i = 0; i < tysize(ty) / 4; ++i)
{
cdb.genc2(PINSRW,modregxrmx(3,reg-XMM0,r),i);
checkSetVex(cdb.last(), TYshort8);
}
if (tysize(ty) == 32)
{
// VINSERTF128 YMM0,YMM0,XMM0,1
cs.Iop = VINSERTF128;
cs.Irm = modregxrmx(3,reg-XMM0,reg-XMM0);
cs.Iflags = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vsize_t = 1;
checkSetVex(&cs,ty);
cdb.gen(&cs);
}
else
{
// VPSHUFD XMM0,XMM0,0
cs.Iop = PSHUFD;
cs.Irm = modregxrmx(3,reg-XMM0,reg-XMM0);
cs.Iflags = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vsize_t = 0;
checkSetVex(&cs,ty);
cdb.gen(&cs);
}
}
else
{
/* MOVD XMM0,r
* PUNPCKLWD XMM0,XMM0
* PSHUFD XMM0,XMM0,0
*/
c = allocreg(&retregs,®, e->Ety);
cdb.append(c);
reg -= XMM0;
cdb.gen2(LODD,modregxrmx(3,reg,r)); // MOVD reg,r
checkSetVex(cdb.last(),e->Ety);
cs.Iop = PUNPCKLWD;
cs.Irm = modregxrmx(3,reg,reg);
cs.Iflags = 0;
cdb.gen(&cs);
cs.Iop = PSHUFD;
cs.IFL2 = FLconst;
cs.IEV2.Vsize_t = 0;
cdb.gen(&cs);
}
break;
}
case TYlong8:
case TYulong8:
case TYlong4:
case TYulong4:
{
if (config.avx &&
((e1->Eoper == OPind && !e1->Ecount) || e1->Eoper == OPvar && !isregvar(e1,&varregm,&varreg)) ||
tysize(ty) == 32 && !isregvar(e1,&varregm,&varreg))
{
goto Lint;
}
/* MOVD XMM1,r
* PSHUFD XMM0,XMM1,0
*/
regm_t regm = ALLREGS;
c = codelem(e1,®m,FALSE); // eval left leaf
cdb.append(c);
unsigned r = findreg(regm);
c = allocreg(&retregs,®, e->Ety);
cdb.append(c);
reg -= XMM0;
cdb.gen2(LODD,modregxrmx(3,reg,r)); // MOVD reg,r
cs.Iop = PSHUFD;
cs.Irm = modregxrmx(3,reg,reg);
cs.Iflags = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vsize_t = 0;
if (config.avx >= 2 || tysize(ty) == 32)
{
// VBROADCASTSS XMM,XMM
cs.Iop = VBROADCASTSS;
checkSetVex(&cs, ty);
}
cdb.gen(&cs);
break;
}
case TYllong2:
case TYullong2:
case TYllong4:
case TYullong4:
if (config.avx || tysize(ty) >= 32)
{
if (e1->Eoper == OPvar)
e1->EV.sp.Vsym->Sflags &= ~GTregcand;
// VMOVDDUP XMM,MEM
cdb.append(getlvalue(&cs, e1, 0)); // get addressing mode
if ((cs.Irm & 0xC0) == 0xC0)
{
unsigned sreg = ((cs.Irm & 7) | (cs.Irex & REX_B ? 8 : 0));
regm_t sregm = XMMREGS;
cdb.append(fixresult(e1, mask[sreg], &sregm));
unsigned rmreg = findreg(sregm);
cs.Irm = (cs.Irm & ~7) | ((rmreg - XMM0) & 7);
if ((rmreg - XMM0) & 8)
cs.Irex |= REX_B;
else
cs.Irex &= ~REX_B;
}
cdb.append(allocreg(&retregs,®,ty));
if (config.avx >= 2 || tysize(ty) >= 32)
{
cs.Iop = VBROADCASTSD;
cs.Irex &= ~REX_W;
}
else
cs.Iop = MOVDDUP;
code_newreg(&cs,reg - XMM0);
checkSetVex(&cs,ty);
cdb.gen(&cs);
}
else
{
/* MOVQ XMM0,mem128
* PUNPCKLQDQ XMM0,XMM0
*/
c = codelem(e1,&retregs,FALSE); // eval left leaf
cdb.append(c);
unsigned reg = findreg(retregs);
reg -= XMM0;
//cdb.gen2(LODD,modregxrmx(3,reg,r)); // MOVQ reg,r
cs.Iop = PUNPCKLQDQ;
cs.Irm = modregxrmx(3,reg,reg);
cs.Iflags = 0;
cdb.gen(&cs);
}
break;
default:
assert(0);
}
c = fixresult(e,retregs,pretregs);
cdb.append(c);
return cdb.finish();
}
code *nteh_prolog()
{
code cs;
code *c1;
code *c;
if (usednteh & NTEHpassthru)
{
/* An sindex value of -2 is a magic value that tells the
* stack unwinder to skip this frame.
*/
assert(config.exe & (EX_LINUX | EX_LINUX64 | EX_OSX | EX_OSX64 | EX_FREEBSD | EX_FREEBSD64 | EX_SOLARIS | EX_SOLARIS64));
cs.Iop = 0x68;
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vint = -2;
return gen(CNIL,&cs); // PUSH -2
}
/* Generate instance of struct __nt_context on stack frame:
[ ] // previous ebp already there
push -1 // sindex
mov EDX,FS:__except_list
push offset FLAT:scope_table // stable (not for MARS or C++)
push offset FLAT:__except_handler3 // handler
push EDX // prev
mov FS:__except_list,ESP
sub ESP,8 // info, esp for __except support
*/
// useregs(mAX); // What is this for?
cs.Iop = 0x68;
cs.Iflags = 0;
cs.Irex = 0;
cs.IFL2 = FLconst;
cs.IEV2.Vint = -1;
c1 = gen(CNIL,&cs); // PUSH -1
if (usednteh & NTEHcpp || MARS)
{
// PUSH &framehandler
cs.IFL2 = FLframehandler;
#if MARS
nteh_scopetable();
#endif
}
else
{
// Do stable
cs.Iflags |= CFoff;
cs.IFL2 = FLextern;
cs.IEVsym2 = nteh_scopetable();
cs.IEVoffset2 = 0;
c1 = gen(c1,&cs); // PUSH &scope_table
cs.IFL2 = FLextern;
cs.IEVsym2 = rtlsym[RTLSYM_EXCEPT_HANDLER3];
makeitextern(rtlsym[RTLSYM_EXCEPT_HANDLER3]);
}
c = gen(NULL,&cs); // PUSH &__except_handler3
if (config.exe == EX_NT)
{
makeitextern(rtlsym[RTLSYM_EXCEPT_LIST]);
#if 0
cs.Iop = 0xFF;
cs.Irm = modregrm(0,6,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = rtlsym[RTLSYM_EXCEPT_LIST];
cs.IEVoffset1 = 0;
gen(c,&cs); // PUSH FS:__except_list
#else
useregs(mDX);
cs.Iop = 0x8B;
cs.Irm = modregrm(0,DX,BPRM);
cs.Iflags = CFfs;
cs.Irex = 0;
cs.IFL1 = FLextern;
cs.IEVsym1 = rtlsym[RTLSYM_EXCEPT_LIST];
cs.IEVoffset1 = 0;
gen(c1,&cs); // MOV EDX,FS:__except_list
gen1(c,0x50 + DX); // PUSH EDX
#endif
cs.Iop = 0x89;
NEWREG(cs.Irm,SP);
gen(c,&cs); // MOV FS:__except_list,ESP
}
c = genc2(c,0x81,modregrm(3,5,SP),8); // SUB ESP,8
return cat(c1,c);
}