/* ************************************************************************ * * Setup the architecture * */ static void __init mpc83xx_km_setup_arch(void) { #ifdef CONFIG_QUICC_ENGINE struct device_node *np; #endif if (ppc_md.progress) ppc_md.progress("kmpbec83xx_setup_arch()", 0); mpc83xx_setup_pci(); #ifdef CONFIG_QUICC_ENGINE np = of_find_node_by_name(NULL, "par_io"); if (np != NULL) { par_io_init(np); of_node_put(np); for_each_node_by_name(np, "spi") par_io_of_config(np); for_each_node_by_name(np, "ucc") par_io_of_config(np); /* Only apply this quirk when par_io is available */ np = of_find_compatible_node(NULL, "network", "ucc_geth"); if (np != NULL) { quirk_mpc8360e_qe_enet10(); of_node_put(np); } } #endif /* CONFIG_QUICC_ENGINE */ }
static void __init sbc834x_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("sbc834x_setup_arch()", 0); mpc83xx_setup_pci(); }
/* * Setup the architecture */ static void __init mpc830x_rdb_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("mpc830x_rdb_setup_arch()", 0); mpc83xx_setup_pci(); mpc831x_usb_cfg(); }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc837x_mds_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("mpc837x_mds_setup_arch()", 0); mpc83xx_setup_pci(); mpc837xmds_usb_cfg(); }
static void __init mpc836x_rdk_setup_arch(void) { if (ppc_md.progress) ppc_md.progress("mpc836x_rdk_setup_arch()", 0); mpc83xx_setup_pci(); #ifdef CONFIG_QUICC_ENGINE qe_reset(); #endif }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc832x_sys_setup_arch(void) { struct device_node *np; u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc832x_sys_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, resource_size(&res)); of_node_put(np); } mpc83xx_setup_pci(); #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ /* Reset the Ethernet PHYs */ #define BCSR8_FETH_RST 0x50 clrbits8(&bcsr_regs[8], BCSR8_FETH_RST); udelay(1000); setbits8(&bcsr_regs[8], BCSR8_FETH_RST); iounmap(bcsr_regs); of_node_put(np); } #endif /* CONFIG_QUICC_ENGINE */ }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc836x_mds_setup_arch(void) { struct device_node *np; u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc836x_mds_setup_arch()", 0); /* Map BCSR area */ np = of_find_node_by_name(NULL, "bcsr"); if (np) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, resource_size(&res)); of_node_put(np); } mpc83xx_setup_pci(); #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); #ifdef CONFIG_QE_USB /* Must fixup Par IO before QE GPIO chips are registered. */ par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */ par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */ par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */ par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */ par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */ par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */ par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */ #endif /* CONFIG_QE_USB */ } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ uint svid; /* Reset the Ethernet PHY */ #define BCSR9_GETHRST 0x20 clrbits8(&bcsr_regs[9], BCSR9_GETHRST); udelay(1000); setbits8(&bcsr_regs[9], BCSR9_GETHRST); /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */ svid = mfspr(SPRN_SVR); if (svid == 0x80480021) { void __iomem *immap; immap = ioremap(get_immrbase() + 0x14a8, 8); /* * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) */ setbits32(immap, 0x0c003000); /* * IMMR + 0x14AC[20:27] = 10101010 * (data delay for both UCC's) */ clrsetbits_be32(immap + 4, 0xff0, 0xaa0); iounmap(immap); } iounmap(bcsr_regs); of_node_put(np); } #endif /* CONFIG_QUICC_ENGINE */ }
static void __init mpc836x_mds_setup_arch(void) { struct device_node *np; u8 __iomem *bcsr_regs = NULL; if (ppc_md.progress) ppc_md.progress("mpc836x_mds_setup_arch()", 0); /* */ np = of_find_node_by_name(NULL, "bcsr"); if (np) { struct resource res; of_address_to_resource(np, 0, &res); bcsr_regs = ioremap(res.start, resource_size(&res)); of_node_put(np); } mpc83xx_setup_pci(); #ifdef CONFIG_QUICC_ENGINE qe_reset(); if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { par_io_init(np); of_node_put(np); for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) par_io_of_config(np); #ifdef CONFIG_QE_USB /* */ par_io_config_pin(1, 2, 1, 0, 3, 0); /* */ par_io_config_pin(1, 3, 1, 0, 3, 0); /* */ par_io_config_pin(1, 8, 1, 0, 1, 0); /* */ par_io_config_pin(1, 10, 2, 0, 3, 0); /* */ par_io_config_pin(1, 9, 2, 1, 3, 0); /* */ par_io_config_pin(1, 11, 2, 1, 3, 0); /* */ par_io_config_pin(2, 20, 2, 0, 1, 0); /* */ #endif /* */ } if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) != NULL){ uint svid; /* */ #define BCSR9_GETHRST 0x20 clrbits8(&bcsr_regs[9], BCSR9_GETHRST); udelay(1000); setbits8(&bcsr_regs[9], BCSR9_GETHRST); /* */ svid = mfspr(SPRN_SVR); if (svid == 0x80480021) { void __iomem *immap; immap = ioremap(get_immrbase() + 0x14a8, 8); /* */ setbits32(immap, 0x0c003000); /* */ clrsetbits_be32(immap + 4, 0xff0, 0xaa0); iounmap(immap); } iounmap(bcsr_regs); of_node_put(np); } #endif /* */ }