void __init mpc83xx_setup_hose(void) { u32 val32; volatile immr_clk_t * clk; struct pci_controller * hose1; #ifdef CONFIG_MPC83xx_PCI2 struct pci_controller * hose2; #endif bd_t * binfo = (bd_t *)__res; clk = ioremap(binfo->bi_immr_base + 0xA00, sizeof(immr_clk_t)); /* * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode */ val32 = clk->occr; udelay(2000); clk->occr = 0xff000000; udelay(2000); iounmap(clk); hose1 = pcibios_alloc_controller(); if(!hose1) return; ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = mpc83xx_map_irq; hose1->bus_offset = 0; hose1->first_busno = 0; hose1->last_busno = 0xff; setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); hose1->set_cfg_type = 1; mpc83xx_setup_pci1(hose1); hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET; hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM; hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM; hose1->io_base_phys = MPC83xx_PCI1_IO_BASE; hose1->io_space.start = MPC83xx_PCI1_LOWER_IO; hose1->io_space.end = MPC83xx_PCI1_UPPER_IO; #ifdef CONFIG_MPC83xx_PCI2 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE); #else isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, MPC83xx_PCI1_IO_SIZE); #endif /* CONFIG_MPC83xx_PCI2 */ hose1->io_base_virt = (void *)isa_io_base; /* setup resources */ pci_init_resource(&hose1->io_resource, MPC83xx_PCI1_LOWER_IO, MPC83xx_PCI1_UPPER_IO, IORESOURCE_IO, "PCI host bridge 1"); pci_init_resource(&hose1->mem_resources[0], MPC83xx_PCI1_LOWER_MEM, MPC83xx_PCI1_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge 1"); ppc_md.pci_exclude_device = mpc83xx_exclude_device; hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); #ifdef CONFIG_MPC83xx_PCI2 hose2 = pcibios_alloc_controller(); if(!hose2) return; hose2->bus_offset = hose1->last_busno + 1; hose2->first_busno = hose1->last_busno + 1; hose2->last_busno = 0xff; setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); hose2->set_cfg_type = 1; mpc83xx_setup_pci2(hose2); hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET; hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM; hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM; hose2->io_base_phys = MPC83xx_PCI2_IO_BASE; hose2->io_space.start = MPC83xx_PCI2_LOWER_IO; hose2->io_space.end = MPC83xx_PCI2_UPPER_IO; hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE); /* setup resources */ pci_init_resource(&hose2->io_resource, MPC83xx_PCI2_LOWER_IO, MPC83xx_PCI2_UPPER_IO, IORESOURCE_IO, "PCI host bridge 2"); pci_init_resource(&hose2->mem_resources[0], MPC83xx_PCI2_LOWER_MEM, MPC83xx_PCI2_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge 2"); hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); #endif /* CONFIG_MPC83xx_PCI2 */ }
void __init mpc83xx_setup_hose(void) { u32 val32; volatile immr_clk_t * clk; volatile law_t * pci_law; struct pci_controller * hose1; #ifdef CONFIG_MPC83xx_PCI2 struct pci_controller * hose2; #endif bd_t * binfo = (bd_t *)__res; u8 val8; clk = ioremap(binfo->bi_immr_base + 0xA00, sizeof(immr_clk_t)); pci_law = ioremap(binfo->bi_immr_base + 0x60, sizeof(law_t)); /* Configure PCI clock drivers */ val32 = clk->occr; udelay(2000); #ifdef CONFIG_CLK_DIV_ENABLE clk->occr = 0xffff0003; #else clk->occr = 0xff000000; #endif udelay(2000); iounmap(clk); /* * Configure PCI Local Access Windows */ pci_law[0].bar = MPC83xx_PCI1_LOWER_MEM & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = MPC83xx_PCI1_IO_BASE & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; iounmap(pci_law); #ifndef CONFIG_MPC834x_ITX /* * Configure PMC <-> PCI by I2C bus */ early_i2c_init(CFG_I2C_SPD,CFG_I2C_SLV); val8 = 0; early_i2c_write(0x23,0x6,1,&val8,1); early_i2c_write(0x23,0x7,1,&val8,1); val8 = 0xff; early_i2c_write(0x23,0x2,1,&val8,1); early_i2c_write(0x23,0x3,1,&val8,1); val8 = 0; early_i2c_write(0x26,0x6,1,&val8,1); val8 = 0x34; early_i2c_write(0x26,0x7,1,&val8,1); #ifdef CONFIG_PCI_64BIT val8 = 0xf4; /* 64bit PMC2<->PCI1 */ #elif defined(CONFIG_PCI_ONE_PCI1) || defined(CONFIG_MPC832XE_MDS) val8 = 0xf9; /* 32bit PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 */ #elif defined(CONFIG_PCI_TWO_PCI1) || defined(CONFIG_MPC8360E_PB) val8 = 0xf7; /* 32bit PMC1<->PCI1,PMC2<->PCI1 PCM3<->PCI2 disabled*/ #else val8 = 0xf3; /* 32bit PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 */ #endif early_i2c_write(0x26,0x2,1,&val8,1); val8 = 0xff; early_i2c_write(0x26,0x3,1,&val8,1); val8 = 0; early_i2c_write(0x27,0x6,1,&val8,1); early_i2c_write(0x27,0x7,1,&val8,1); val8 = 0xff; early_i2c_write(0x27,0x2,1,&val8,1); val8 = 0xef; early_i2c_write(0x27,0x3,1,&val8,1); asm("eieio"); #endif /* CONFIG_MPC834x_ITX */ hose1 = pcibios_alloc_controller(); if(!hose1) return; ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = mpc83xx_map_irq; hose1->bus_offset = 0; hose1->first_busno = 0; hose1->last_busno = 0xff; setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); hose1->ops = &mpc83xx_indirect_pci_ops; mpc83xx_setup_pci1(hose1); hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET; hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM; hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM; hose1->io_base_phys = MPC83xx_PCI1_IO_BASE; hose1->io_space.start = MPC83xx_PCI1_LOWER_IO; hose1->io_space.end = MPC83xx_PCI1_UPPER_IO; #ifdef CONFIG_MPC83xx_PCI2 isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE); #else isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE, MPC83xx_PCI1_IO_SIZE); #endif /* CONFIG_MPC83xx_PCI2 */ hose1->io_base_virt = (void *)isa_io_base; /* setup resources */ pci_init_resource(&hose1->io_resource, MPC83xx_PCI1_LOWER_IO, MPC83xx_PCI1_UPPER_IO, IORESOURCE_IO, "PCI host bridge 1"); pci_init_resource(&hose1->mem_resources[0], MPC83xx_PCI1_LOWER_MEM, MPC83xx_PCI1_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge 1"); ppc_md.pci_exclude_device = mpc83xx_exclude_device; hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); #ifdef CONFIG_MPC83xx_PCI2 hose2 = pcibios_alloc_controller(); if(!hose2) return; hose2->bus_offset = hose1->last_busno + 1; hose2->first_busno = hose1->last_busno + 1; hose2->last_busno = 0xff; setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); hose2->ops = &mpc83xx_indirect_pci_ops; mpc83xx_setup_pci2(hose2); hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET; hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM; hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM; hose2->io_base_phys = MPC83xx_PCI2_IO_BASE; hose2->io_space.start = MPC83xx_PCI2_LOWER_IO; hose2->io_space.end = MPC83xx_PCI2_UPPER_IO; hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE); /* setup resources */ pci_init_resource(&hose2->io_resource, MPC83xx_PCI2_LOWER_IO, MPC83xx_PCI2_UPPER_IO, IORESOURCE_IO, "PCI host bridge 2"); pci_init_resource(&hose2->mem_resources[0], MPC83xx_PCI2_LOWER_MEM, MPC83xx_PCI2_UPPER_MEM, IORESOURCE_MEM, "PCI host bridge 2"); hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); #endif /* CONFIG_MPC83xx_PCI2 */ }