static void __init pSeries_init_mpic(void) { unsigned int *addrp; struct device_node *np; int i; /* All ISUs are setup, complete initialization */ mpic_init(pSeries_mpic); /* Check what kind of cascade ACK we have */ if (!(np = of_find_node_by_name(NULL, "pci")) || !(addrp = (unsigned int *) get_property(np, "8259-interrupt-acknowledge", NULL))) printk(KERN_ERR "Cannot find pci to get ack address\n"); else chrp_int_ack_special = ioremap(addrp[prom_n_addr_cells(np)-1], 1); of_node_put(np); /* Setup the legacy interrupts & controller */ for (i = 0; i < NUM_ISA_INTERRUPTS; i++) irq_desc[i].handler = &i8259_pic; i8259_init(0); /* Hook cascade to mpic */ mpic_setup_cascade(NUM_ISA_INTERRUPTS, pSeries_irq_cascade, NULL); }
static __init void pmac_init_IRQ(void) { struct device_node *irqctrler = NULL; struct device_node *irqctrler2 = NULL; struct device_node *np = NULL; struct mpic *mpic1, *mpic2; /* We first try to detect Apple's new Core99 chipset, since mac-io * is quite different on those machines and contains an IBM MPIC2. */ while ((np = of_find_node_by_type(np, "open-pic")) != NULL) { struct device_node *parent = of_get_parent(np); if (parent && !strcmp(parent->name, "u3")) irqctrler2 = of_node_get(np); else irqctrler = of_node_get(np); of_node_put(parent); } if (irqctrler != NULL && irqctrler->n_addrs > 0) { unsigned char senses[128]; printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n", (unsigned int)irqctrler->addrs[0].address); prom_get_irq_senses(senses, 0, 128); mpic1 = mpic_alloc(irqctrler->addrs[0].address, MPIC_PRIMARY | MPIC_WANTS_RESET, 0, 0, 128, 256, senses, 128, " K2-MPIC "); BUG_ON(mpic1 == NULL); mpic_init(mpic1); if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 && irqctrler2->n_addrs > 0) { printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n", (u32)irqctrler2->addrs[0].address, irqctrler2->intrs[0].line); pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0); prom_get_irq_senses(senses, 128, 128 + 128); /* We don't need to set MPIC_BROKEN_U3 here since we don't have * hypertransport interrupts routed to it */ mpic2 = mpic_alloc(irqctrler2->addrs[0].address, MPIC_BIG_ENDIAN | MPIC_WANTS_RESET, 0, 128, 128, 0, senses, 128, " U3-MPIC "); BUG_ON(mpic2 == NULL); mpic_init(mpic2); mpic_setup_cascade(irqctrler2->intrs[0].line, pmac_u3_cascade, mpic2); } } of_node_put(irqctrler); of_node_put(irqctrler2); }