// Write data
e_MQTTSN_RETURNS_t serWriteOD(subidx_t * pSubidx, uint8_t Len, uint8_t *pBuf)
{
uint8_t port = pSubidx->Base/10;
assert(extSerV[port] != NULL);
if(Len > 0)
{
if((extSerV[port]->pTxBuf == NULL) && hal_uart_free(port))
{
MQ_t * pTxBuf = mqAlloc(sizeof(MQ_t));
if(pTxBuf == NULL)
return MQTTSN_RET_REJ_CONG;
memcpy(pTxBuf->raw, pBuf, Len);
hal_uart_send(port, Len, pTxBuf->raw);
extSerV[port]->pTxBuf = pTxBuf;
}
else
return MQTTSN_RET_REJ_CONG;
}
return MQTTSN_RET_ACCEPTED;
}
void * UART_Get(void)
{
uart_tx_task();
// Rx Task
static uint8_t rx_pos = 0;
static uint8_t rx_len = 0;
static MQ_t * pRx_buf;
static uint16_t rx_wd = 0;
while(hal_uart_datardy(UART_PHY_PORT))
{
uint8_t data = hal_uart_get(UART_PHY_PORT);
rx_wd = (HAL_get_ms() & 0xFFFF);
if(rx_len == 0)
{
if((data >= 2) && (data < sizeof(MQTTSN_MESSAGE_t)))
{
pRx_buf = mqAlloc(sizeof(MQ_t));
rx_len = data;
rx_pos = 0;
}
}
else
{
if(rx_pos < sizeof(MQTTSN_MESSAGE_t))
pRx_buf->m.raw[rx_pos++] = data;
if(rx_pos == rx_len)
{
memcpy(pRx_buf->a.phy1addr, (const void *)&uart_addr, sizeof(UART_ADDR_t));
pRx_buf->Length = rx_len;
rx_len = 0;
#ifdef LED_On
LED_On();
#endif // LED_On
return pRx_buf;
}
}
}
if((rx_len != 0) && (((HAL_get_ms() & 0xFFFF) - rx_wd) > 100))
{
rx_len = 0;
mqFree(pRx_buf);
}
return NULL;
}
void * UART_Get(void)
{
uart_tx_task();
// Rx Task
static uint8_t rx_pos = 0;
static uint8_t rx_len = 0;
static MQ_t * pRx_buf;
static uint32_t rx_wd = 0;
while(hal_uart_datardy(UART_PHY_PORT))
{
uint8_t data = hal_uart_get(UART_PHY_PORT);
rx_wd = hal_get_ms() + 50;
if(rx_len == 0)
{
if(data >= 2)
{
pRx_buf = mqAlloc(sizeof(MQ_t));
if(pRx_buf != NULL)
rx_len = data;
rx_pos = 0;
}
}
else
{
if(rx_pos < sizeof(MQTTSN_MESSAGE_t))
pRx_buf->raw[rx_pos++] = data;
if(rx_pos == rx_len)
{
memcpy(pRx_buf->phy1addr, (const void *)&uart_addr, sizeof(UART_ADDR_t));
pRx_buf->Length = rx_len;
rx_len = 0;
Activity(UART_PHY);
return pRx_buf;
}
}
}
if((rx_len != 0) && (rx_wd < hal_get_ms()))
rx_len = 0;
return NULL;
}
void hal_uart_init_hw(uint8_t port, uint8_t nBaud, uint8_t enable)
{
volatile uint8_t * pPort;
switch(port)
{
#ifdef HAL_USE_USART0
case HAL_USE_USART0:
pPort = &UCSR0A;
if(enable & 1) // Rx
{
UART0_PORT |= (1<<UART0_RX_PIN);
UART0_DDR &= ~(1<<UART0_RX_PIN);
}
if(enable & 2) // Tx
{
UART0_PORT |= (1<<UART0_TX_PIN);
UART0_DDR |= (1<<UART0_TX_PIN);
}
break;
#endif // HAL_USE_USART0
#if (defined HAL_USE_USART1)
case HAL_USE_USART1:
pPort = &UCSR1A;
if(enable & 1) // Rx
{
UART1_PORT |= (1<<UART1_RX_PIN);
UART1_DDR &= ~(1<<UART1_RX_PIN);
}
if(enable & 2) // Tx
{
UART1_PORT |= (1<<UART1_TX_PIN);
UART1_DDR |= (1<<UART1_TX_PIN);
}
break;
#endif // HAL_USE_USART1
#if (defined HAL_USE_USART2)
case HAL_USE_USART2:
pPort = &UCSR2A;
if(enable & 1) // Rx
{
UART2_PORT |= (1<<UART2_RX_PIN);
UART2_DDR &= ~(1<<UART2_RX_PIN);
}
if(enable & 2) // Tx
{
UART2_PORT |= (1<<UART2_TX_PIN);
UART2_DDR |= (1<<UART2_TX_PIN);
}
break;
#endif // HAL_USE_USART2
#if (defined HAL_USE_USART3)
case HAL_USE_USART3:
pPort = &UCSR3A;
if(enable & 1) // Rx
{
UART3_PORT |= (1<<UART3_RX_PIN);
UART3_DDR &= ~(1<<UART3_RX_PIN);
}
if(enable & 2) // Tx
{
UART3_PORT |= (1<<UART3_TX_PIN);
UART3_DDR |= (1<<UART3_TX_PIN);
}
break;
#endif // HAL_USE_USART3
// Port not exist
default:
while(1);
}
if(hal_UARTv[port] == NULL)
{
hal_UARTv[port] = mqAlloc(sizeof(HAL_UART_t));
hal_UARTv[port]->rx_head = 0;
hal_UARTv[port]->rx_tail = 0;
hal_UARTv[port]->tx_len = 0;
hal_UARTv[port]->tx_pos = 0;
uint16_t baud = pgm_read_word(&hal_baud_list[nBaud]);
*(pPort + 5) = (baud >> 8); // UBRRH
*(pPort + 4) = (baud & 0xFF); // UBRRL
*(pPort + 1) = 0; // UCSRB
*(pPort + 2) = (3<<UCSZ00); // UCSRC
}
// Register Object
e_MQTTSN_RETURNS_t serRegisterOD(indextable_t *pIdx)
{
uint8_t port = pIdx->sidx.Base / 10;
uint8_t nBaud = pIdx->sidx.Base % 10;
eObjTyp_t type = pIdx->sidx.Type;
uint8_t TxPin, RxPin;
hal_uart_get_pins(port, &RxPin, &TxPin);
if(type == ObjSerTx)
{
if(dioCheckBase(TxPin) != 0)
return MQTTSN_RET_REJ_INV_ID;
}
else
{
if(dioCheckBase(RxPin) == 2)
return MQTTSN_RET_REJ_INV_ID;
}
if(extSerV[port] != NULL)
{
if(extSerV[port]->nBaud != nBaud)
return MQTTSN_RET_REJ_INV_ID;
if(type == ObjSerTx)
{
if(extSerV[port]->flags & EXTSER_FLAG_TXEN)
return MQTTSN_RET_REJ_INV_ID;
}
else
{
if(extSerV[port]->flags & EXTSER_FLAG_RXEN)
return MQTTSN_RET_REJ_INV_ID;
}
}
else
{
extSerV[port] = mqAlloc(sizeof(EXTSER_VAR_t));
if(extSerV[port] == NULL)
return MQTTSN_RET_REJ_CONG;
extSerV[port]->nBaud = nBaud;
extSerV[port]->flags = 0;
extSerV[port]->pRxBuf = NULL;
extSerV[port]->RxHead = 0;
extSerV[port]->RxTail = 0;
extSerV[port]->pTxBuf = NULL;
}
if(type == ObjSerTx)
{
extSerV[port]->flags |= EXTSER_FLAG_TXEN;
pIdx->cbWrite = &serWriteOD;
dioTake(TxPin);
hal_uart_init_hw(port, nBaud, 2);
}
else // ObjSerRx
{
if(extSerV[port]->pRxBuf == NULL)
{
extSerV[port]->pRxBuf = mqAlloc(sizeof(MQ_t));
if(extSerV[port]->pRxBuf == NULL)
return MQTTSN_RET_REJ_CONG;
}
extSerV[port]->flags |= EXTSER_FLAG_RXEN;
pIdx->cbRead = &serReadOD;
pIdx->cbPoll = &serPollOD;
dioTake(RxPin);
hal_uart_init_hw(port, nBaud, 1);
}
return MQTTSN_RET_ACCEPTED;
}
// enable bit 0 - Rx, 1 - Tx
void hal_uart_init_hw(uint8_t port, uint8_t nBaud, uint8_t enable)
{
assert(nBaud < 5)
USART_TypeDef * USARTx;
IRQn_Type UARTx_IRQn;
RCC_ClocksTypeDef RCC_ClocksStatus;
uint32_t uart_clock;
uint16_t baud = hal_baud_list[nBaud];
RCC_GetClocksFreq(&RCC_ClocksStatus);
#if (defined HAL_USE_USART1)
if(port == HAL_USE_USART1)
{
#if (defined __STM32F0XX_H)
uart_clock = RCC_ClocksStatus.USART1CLK_Frequency;
#else
uart_clock = RCC_ClocksStatus.PCLK2_Frequency;
#endif
}
else // USART2/3 UART4/5
#endif // HAL_USE_USART1
{
#if (defined __STM32F0XX_H)
uart_clock = RCC_ClocksStatus.PCLK_Frequency;
#else
uart_clock = RCC_ClocksStatus.PCLK1_Frequency;
#endif
}
switch(port)
{
#if (defined HAL_USE_USART1)
case HAL_USE_USART1:
{
USARTx = USART1;
UARTx_IRQn = USART1_IRQn;
RCC->APB2ENR |= RCC_APB2ENR_USART1EN; // Enable UART1 Clock
#ifndef __STM32F10x_H
if(enable & 1) // Enable Rx
#if (defined HAL_USE_ALT_USART1)
hal_dio_gpio_cfg(GPIOB, GPIO_Pin_7, HAL_USART1_ALT_AF); // PB7(Rx)
#else
hal_dio_gpio_cfg(GPIOA, GPIO_Pin_10, HAL_USART1_AF); // PA10(Rx)
#endif // HAL_USE_ALT_USART1
#endif // __STM32F10x_H
if(enable & 2) // Enable Tx
#if (defined HAL_USE_ALT_USART1)
hal_dio_gpio_cfg(GPIOB, GPIO_Pin_6, HAL_USART1_ALT_AF); // PB6(Tx)
#else
hal_dio_gpio_cfg(GPIOA, GPIO_Pin_9, HAL_USART1_AF); // PA9(Tx)
#endif // HAL_USE_ALT_USART1
}
break;
#endif // USART1
#if (defined HAL_USE_USART2)
case HAL_USE_USART2:
{
USARTx = USART2;
UARTx_IRQn = USART2_IRQn;
RCC->APB1ENR |= RCC_APB1ENR_USART2EN; // Enable UART2 Clock
#ifndef __STM32F10x_H
if(enable & 1) // Enable Rx
hal_dio_gpio_cfg(GPIOA, GPIO_Pin_3, HAL_USART2_AF); // PA3(Rx)
#endif // __STM32F10x_H
if(enable & 2) // Enable Tx
hal_dio_gpio_cfg(GPIOA, GPIO_Pin_2, HAL_USART2_AF); // PA2(Tx) - AF1
}
break;
#endif // USART2
#if (defined HAL_USE_USART3)
case HAL_USE_USART3:
{
USARTx = USART3;
UARTx_IRQn = USART3_IRQn;
RCC->APB1ENR |= RCC_APB1ENR_USART3EN; // Enable UART3 Clock
#ifndef __STM32F10x_H
if(enable & 1) // Enable Rx
hal_dio_gpio_cfg(GPIOB, GPIO_Pin_11, HAL_USART3_AF); // PB11(Rx)
#endif // __STM32F10x_H
if(enable & 2) // Enable Tx
hal_dio_gpio_cfg(GPIOB, GPIO_Pin_10, HAL_USART3_AF); // PB10(Tx)
}
break;
#endif // USART3
#if (defined HAL_USE_UART4)
case HAL_USE_UART4:
{
USARTx = UART4;
UARTx_IRQn = UART4_IRQn;
RCC->APB1ENR |= RCC_APB1ENR_UART4EN; // Enable UART4 Clock
if(enable & 1) // Enable Rx
hal_dio_gpio_cfg(GPIOA, GPIO_Pin_1, HAL_UART4_AF); // PA1(Rx)
if(enable & 2) // Enable Tx
hal_dio_gpio_cfg(GPIOA, GPIO_Pin_0, HAL_UART4_AF); // PA0(Tx)
}
break;
#endif // UART4
default:
assert(0);
}
if(hal_UARTv[port] == NULL)
{
hal_UARTv[port] = mqAlloc(sizeof(HAL_UART_t));
assert(hal_UARTv[port] != NULL);
}
if(USARTx->CR1 & USART_CR1_UE)
{
USARTx->CR1 &= ~USART_CR1_UE;
}
else
{
hal_UARTv[port]->rx_head = 0;
hal_UARTv[port]->rx_tail = 0;
hal_UARTv[port]->pTxBuf = NULL;
hal_UARTv[port]->tx_len = 0;
hal_UARTv[port]->tx_pos = 0;
USARTx->CR1 = 0; // Disable USART1
USARTx->CR2 = 0; // 8N1
USARTx->CR3 = 0; // Without flow control
USARTx->BRR = ((uart_clock + baud/2)/baud); // Speed
}
if(enable & 1) // Enable Rx
USARTx->CR1 |= USART_CR1_RE | // Enable RX
USART_CR1_RXNEIE; // Enable RX Not Empty IRQ
if(enable & 2) // Enable Tx
USARTx->CR1 |= USART_CR1_TE; // Enable TX
NVIC_EnableIRQ(UARTx_IRQn); // Enable UASRT IRQ
USARTx->CR1 |= USART_CR1_UE; // Enable USART
}
