void platform_simrf_init(void) {
mrf_gpio_setup();
spi_setup();
plat_select(false);
struct simrf_platform plat;
memset(&plat, 0, sizeof(plat));
plat.select = &plat_select;
plat.reset = NULL; // Not connected on this board
plat.spi_xfr = &plat_spi_tx;
plat.delay_ms = &delay_ms;
// TODO more here!
simrf_setup(&plat);
}
static
int __devinit
mrf_probe(struct pci_dev *dev,
const struct pci_device_id *id)
{
int ret = -ENODEV;
struct mrf_priv *priv;
struct uio_info *info;
priv = kzalloc(sizeof(struct mrf_priv), GFP_KERNEL);
if (!priv) return -ENOMEM;
info = &priv->uio;
priv->pdev = dev;
ret = pci_enable_device(dev);
if (ret) {
dev_err(&dev->dev, "pci_enable_device failed with %d\n",ret);
goto err_free;
}
if (!dev->irq) {
dev_warn(&dev->dev, "Device not configured with IRQ!\n");
ret=-ENODEV;
goto err_disable;
}
if (pci_request_regions(dev, DRV_NAME))
goto err_disable;
/* BAR 0 is the PLX bridge */
info->mem[0].addr = pci_resource_start(dev, 0);
info->mem[0].size = pci_resource_len(dev,0);
info->mem[0].internal_addr =pci_ioremap_bar(dev,0);
info->mem[0].memtype = UIO_MEM_PHYS;
/* Not used */
info->mem[1].memtype = UIO_MEM_NONE;
info->mem[1].size = 1; /* Otherwise UIO will stop searching... */
/* BAR 2 is the EVR */
info->mem[2].addr = pci_resource_start(dev, 2);
info->mem[2].size = pci_resource_len(dev,2);
info->mem[2].internal_addr =pci_ioremap_bar(dev,2);
info->mem[2].memtype = UIO_MEM_PHYS;
if (!info->mem[0].internal_addr ||
!info->mem[0].addr ||
!info->mem[2].internal_addr ||
!info->mem[2].addr) {
dev_err(&dev->dev, "Failed to map BARS!\n");
ret=-ENODEV;
goto err_release;
}
info->irq = dev->irq;
info->irq_flags = IRQF_SHARED;
info->handler = mrf_handler;
info->irqcontrol = mrf_irqcontrol;
#ifdef USE_CUSTOM_MMAP
info->mmap = mrf_mmap_physical;
#endif
info->name = DRV_NAME;
info->version = DRV_VERSION;
info->priv = dev;
pci_set_drvdata(dev, info);
ret = uio_register_device(&dev->dev, info);
if (ret)
goto err_unmap;
#if defined(CONFIG_GENERIC_GPIO) || defined(CONFIG_PARPORT_NOT_PC)
spin_lock_init(&priv->lock);
if (dev->device==PCI_DEVICE_ID_PLX_9030) {
u32 val;
void __iomem *plx = info->mem[0].internal_addr;
/* GPIO Bits 0-3 are used as GPIO for JTAG.
* Bits 4-7 must be left to their normal functions.
* The device is expected to configure bits 4-7
* itself when initialized, and not change them
* afterward. So we just avoid changes.
*
* Power up value observed in a PMC-EVR-230
* GPIOC = 0x00249924
* is consistent with the default given in the
* PLX 9030 data book.
*/
val = ioread32(plx + GPIOC);
/* clear everything for GPIO 0-3 (aka first 12 bits).
* Preserve current settings for GPIO 4-7.
* This will setup these as inputs (which float high)
*
* Each GPIO bit has 3 register bits (function, direction, and value)
*/
val &= 0xfffff000;
// Enable output drivers for TCLK, TMS, and TDI
val |= GPIOC_pin_dir(0);
val |= GPIOC_pin_dir(1);
val |= GPIOC_pin_dir(3);
dev_info(&dev->dev, "GPIOC %08x\n", val);
iowrite32(val, plx + GPIOC);
#ifdef CONFIG_GENERIC_GPIO
mrf_gpio_setup(priv);
#endif
#ifdef CONFIG_PARPORT_NOT_PC
mrf_pp_setup(priv);
#endif
}
#else
if (dev->device==PCI_DEVICE_ID_PLX_9030)
dev_info(&dev->dev, "GPIO support not built, JTAG unavailable\n");
#endif /* defined(CONFIG_GENERIC_GPIO) || defined(CONFIG_PARPORT_NOT_PC) */
dev_info(&dev->dev, "MRF Setup complete\n");
return 0;
//err_unreg:
// uio_unregister_device(info);
// pci_set_drvdata(dev, NULL);
err_unmap:
iounmap(info->mem[0].internal_addr);
iounmap(info->mem[2].internal_addr);
err_release:
pci_release_regions(dev);
err_disable:
pci_disable_device(dev);
err_free:
kzfree(priv);
return ret;
}
