예제 #1
0
static int msm8x16_enable_codec_ext_clk(struct snd_soc_codec *codec,
					int enable, bool dapm)
{
	int ret = 0;

	mutex_lock(&cdc_mclk_mutex);

	pr_debug("%s: enable = %d  codec name %s enable %d mclk ref counter %d\n",
		   __func__, enable, codec->name, enable,
		   atomic_read(&mclk_rsc_ref));
	if (enable) {
		if (atomic_inc_return(&mclk_rsc_ref) == 1) {
			digital_cdc_clk.clk_val = 9600000;
			msm_config_mclk(AFE_PORT_ID_SECONDARY_MI2S_RX,
					&digital_cdc_clk);
			msm8x16_wcd_mclk_enable(codec, 1, dapm);
		}
	} else {
		if (atomic_dec_return(&mclk_rsc_ref) == 0) {
			digital_cdc_clk.clk_val = 0;
			msm8x16_wcd_mclk_enable(codec, 0, dapm);
			msm_config_mclk(AFE_PORT_ID_SECONDARY_MI2S_RX,
					&digital_cdc_clk);
		}
	}
	mutex_unlock(&cdc_mclk_mutex);
	return ret;
}
예제 #2
0
static int msm_config_mi2s_clk(int enable)
{
	int ret = 0;
	pr_debug("%s(line %d):enable = %x\n", __func__, __LINE__, enable);
	if (enable) {
		digital_cdc_clk.clk_val = 9600000;
		mi2s_rx_clk.clk_val2 = Q6AFE_LPASS_OSR_CLK_12_P288_MHZ;
		mi2s_rx_clk.clk_val1 = Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ;
		ret = afe_set_lpass_clock(AFE_PORT_ID_SECONDARY_MI2S_RX,
					  &mi2s_rx_clk);
		mi2s_tx_clk.clk_val2 = Q6AFE_LPASS_OSR_CLK_12_P288_MHZ;
		mi2s_tx_clk.clk_val1 = Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ;
		ret = afe_set_lpass_clock(AFE_PORT_ID_PRIMARY_MI2S_RX,
					  &mi2s_tx_clk);
		if (ret < 0)
			pr_err("%s:afe_set_lpass_clock failed\n", __func__);

	} else {
		digital_cdc_clk.clk_val = 0;
		mi2s_rx_clk.clk_val2 = Q6AFE_LPASS_OSR_CLK_DISABLE;
		mi2s_rx_clk.clk_val1 = Q6AFE_LPASS_IBIT_CLK_DISABLE;
		ret = afe_set_lpass_clock(AFE_PORT_ID_SECONDARY_MI2S_RX,
					  &mi2s_rx_clk);
		mi2s_tx_clk.clk_val2 = Q6AFE_LPASS_OSR_CLK_DISABLE;
		mi2s_tx_clk.clk_val1 = Q6AFE_LPASS_IBIT_CLK_DISABLE;
		ret = afe_set_lpass_clock(AFE_PORT_ID_PRIMARY_MI2S_RX,
					  &mi2s_tx_clk);
		if (ret < 0)
			pr_err("%s:afe_set_lpass_clock failed\n", __func__);

	}
	ret = msm_config_mclk(AFE_PORT_ID_SECONDARY_MI2S_RX, &digital_cdc_clk);
	return ret;
}
예제 #3
0
static int msm8x10_enable_codec_ext_clk(struct snd_soc_codec *codec,
					int enable, bool dapm)
{
	int ret = 0;

	pr_debug("%s: enable = %d  codec name %s enable %x\n",
		   __func__, enable, codec->name, enable);
	if (enable) {
		digital_cdc_clk.clk_val = 9600000;
		msm_config_mi2s_clk(1);
		ret = msm_config_mclk(AFE_PORT_ID_SECONDARY_MI2S_RX,
					   &digital_cdc_clk);
		msm8x10_wcd_mclk_enable(codec, 1, dapm);
	} else {
		msm8x10_wcd_mclk_enable(codec, 0, dapm);
		ret = msm_config_mclk(AFE_PORT_ID_SECONDARY_MI2S_RX,
					   &digital_cdc_clk);
		msm_config_mi2s_clk(0);
	}
	return ret;
}
예제 #4
0
static int mi2s_clk_ctl(struct snd_pcm_substream *substream, bool enable)
{
	int ret = 0;
	if (enable) {
		digital_cdc_clk.clk_val = 9600000;
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			mi2s_rx_clk.clk_val2 = Q6AFE_LPASS_OSR_CLK_12_P288_MHZ;
			mi2s_rx_clk.clk_val1 = Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ;
			ret = afe_set_lpass_clock(AFE_PORT_ID_SECONDARY_MI2S_RX,
						  &mi2s_rx_clk);
		} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
			mi2s_tx_clk.clk_val2 = Q6AFE_LPASS_OSR_CLK_12_P288_MHZ;
			mi2s_tx_clk.clk_val1 = Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ;
			ret = afe_set_lpass_clock(AFE_PORT_ID_PRIMARY_MI2S_RX,
						  &mi2s_tx_clk);
		} else
			pr_err("%s:Not valid substream.\n", __func__);

		if (ret < 0)
			pr_err("%s:afe_set_lpass_clock failed\n", __func__);

	} else {
		digital_cdc_clk.clk_val = 0;
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			mi2s_rx_clk.clk_val2 = Q6AFE_LPASS_OSR_CLK_DISABLE;
			mi2s_rx_clk.clk_val1 = Q6AFE_LPASS_IBIT_CLK_DISABLE;
			ret = afe_set_lpass_clock(AFE_PORT_ID_SECONDARY_MI2S_RX,
						  &mi2s_rx_clk);
		} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
			mi2s_tx_clk.clk_val2 = Q6AFE_LPASS_OSR_CLK_DISABLE;
			mi2s_tx_clk.clk_val1 = Q6AFE_LPASS_IBIT_CLK_DISABLE;
			ret = afe_set_lpass_clock(AFE_PORT_ID_PRIMARY_MI2S_RX,
						  &mi2s_tx_clk);
		} else
			pr_err("%s:Not valid substream.\n", __func__);

		if (ret < 0)
			pr_err("%s:afe_set_lpass_clock failed\n", __func__);

	}
	ret = msm_config_mclk(AFE_PORT_ID_SECONDARY_MI2S_RX, &digital_cdc_clk);
	return ret;
}