static int msm_hsl_startup_cir(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
unsigned int data, rfr_level;
unsigned int vid;
int ret;
unsigned long flags;
snprintf(msm_hsl_port->name, sizeof(msm_hsl_port->name),
"msm_serial_hsl%d", port->line);
D("%s () :port->line %d, ir\n", __func__, port->line);
if (!(is_console(port)) || (!port->cons) ||
(port->cons && (!(port->cons->flags & CON_ENABLED)))) {
if (msm_serial_hsl_has_gsbi(port)) {
D("%s () serial_hsl_has_gsbi:port->line %d, ir\n", __func__, port->line);
if ((ioread32(msm_hsl_port->mapped_gsbi +
GSBI_CONTROL_ADDR) & GSBI_PROTOCOL_I2C_UART)
!= GSBI_PROTOCOL_I2C_UART){
D("%s () iowrite32i:port->line %d, ir\n", __func__, port->line);
iowrite32(GSBI_PROTOCOL_I2C_UART,
msm_hsl_port->mapped_gsbi +
GSBI_CONTROL_ADDR);
}
}
}
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_get_sync(port->dev);
if (likely(port->fifosize > 48))
rfr_level = port->fifosize - 16;
else
rfr_level = port->fifosize;
rfr_level = (rfr_level / 4);
spin_lock_irqsave(&port->lock, flags);
vid = msm_hsl_port->ver_id;
data = msm_hsl_read(port, regmap[vid][UARTDM_MR1]);
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
data |= UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2);
data |= UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level;
msm_hsl_write(port, data, regmap[vid][UARTDM_MR1]);
spin_unlock_irqrestore(&port->lock, flags);
ret = request_irq(port->irq, msm_hsl_irq, IRQF_TRIGGER_HIGH,
msm_hsl_port->name, port);
if (unlikely(ret)) {
printk(KERN_ERR "%s: failed to request_irq\n", __func__);
return ret;
}
return 0;
}
static int msm_serial_hsl_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct msm_hsl_port *msm_cir_port = htc_cir_port;
struct uart_port *port;
port = get_port_from_line(pdev->id);
D("%s ():port->line %d, cir_enable_flg = %d\n",
__func__, port->line, cir_enable_flg);
if (msm_cir_port->cir_power)
msm_cir_port->cir_power(1);
if (port) {
if (msm_cir_port->cir_set_path)
msm_cir_port->cir_set_path(cir_enable_flg);
uart_resume_port(&msm_hsl_uart_driver, port);
if (device_may_wakeup(dev))
disable_irq_wake(port->irq);
if (is_console(port))
msm_hsl_init_clock(port);
}
return 0;
}
static int msm_hsl_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct uart_port *port;
port = get_port_from_line(pdev->id);
dev_dbg(dev, "pm_runtime: resuming\n");
msm_hsl_init_clock(port);
return 0;
}
static int msm_hsl_console_setup(struct console *co, char *options)
{
struct uart_port *port;
unsigned int vid;
int baud = 0, flow, bits, parity;
int ret;
pr_info("%s: ir\n", __func__);
if (unlikely(co->index >= UART_NR || co->index < 0))
return -ENXIO;
port = get_port_from_line(co->index);
vid = UART_TO_MSM(port)->ver_id;
pr_info("%s ():port->line %d, ir\n", __func__, port->line);
if (unlikely(!port->membase))
return -ENXIO;
port->cons = co;
pm_runtime_get_noresume(port->dev);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_resume(port->dev);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
bits = 8;
parity = 'n';
flow = 'n';
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
regmap[vid][UARTDM_MR2]);
if (baud < 300 || baud > 115200)
baud = 115200;
msm_hsl_set_baud_rate(port, baud);
pr_info("%s: cir port[%d] set baud=%d\n", __func__, port->line, baud);
ret = uart_set_options(port, co, baud, parity, bits, flow);
msm_hsl_reset(port);
msm_hsl_write(port, CR_PROTECTION_EN, regmap[vid][UARTDM_CR]);
msm_hsl_write(port, UARTDM_CR_TX_EN_BMSK, regmap[vid][UARTDM_CR]);
printk(KERN_INFO "msm_serial_hsl: console setup on port #%d\n",
port->line);
pr_info("%s ():port->line %d, ok, ir\n", __func__, port->line);
return ret;
}
static int __init msm_hsl_console_setup(struct console *co, char *options)
{
struct uart_port *port;
int baud, flow, bits, parity;
int ret;
if (unlikely(co->index >= UART_NR || co->index < 0))
return -ENXIO;
port = get_port_from_line(co->index);
if (unlikely(!port->membase))
return -ENXIO;
port->cons = co;
pm_runtime_get_noresume(port->dev);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_resume(port->dev);
if (options)
uart_parse_options(options, &baud, &parity, &bits, &flow);
bits = 8;
parity = 'n';
flow = 'n';
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
UARTDM_MR2_ADDR); /* 8N1 */
if (baud < 300 || baud > 115200)
baud = 115200;
msm_hsl_set_baud_rate(port, baud);
ret = uart_set_options(port, co, baud, parity, bits, flow);
msm_hsl_reset(port);
/* Enable transmitter */
msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
msm_hsl_write(port, UARTDM_CR_TX_EN_BMSK, UARTDM_CR_ADDR);
printk(KERN_INFO "msm_serial_hsl: console setup on port #%d\n",
port->line);
console_uart_port = port;
b_terminal_onoff = 0;
return ret;
}
static int msm_serial_hsl_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct uart_port *port;
port = get_port_from_line(pdev->id);
if (port) {
if (is_console(port))
msm_hsl_init_clock(port);
uart_resume_port(&msm_hsl_uart_driver, port);
if (device_may_wakeup(dev))
disable_irq_wake(port->irq);
}
return 0;
}
static int msm_serial_hsl_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct msm_hsl_port *msm_cir_port = htc_cir_port;
struct uart_port *port;
port = get_port_from_line(pdev->id);
pr_info("[CIR] %s ():port->line %d, ir\n", __func__, port->line);
if(power_state == 1)
msm_cir_port->power(1);
if (port) {
pr_info("%s ():uart_resume_port:port->line %d, ir\n", __func__, port->line);
enable_cir(3);
uart_resume_port(&msm_hsl_uart_driver, port);
if (device_may_wakeup(dev))
disable_irq_wake(port->irq);
if (is_console(port))
msm_hsl_init_clock(port);
}
return 0;
}
static int msm_hsl_startup(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
struct platform_device *pdev = to_platform_device(port->dev);
const struct msm_serial_hslite_platform_data *pdata =
pdev->dev.platform_data;
unsigned int data, rfr_level;
int ret;
unsigned long flags;
snprintf(msm_hsl_port->name, sizeof(msm_hsl_port->name),
"msm_serial_hsl%d", port->line);
if (!(is_console(port)) || (!port->cons) ||
(port->cons && (!(port->cons->flags & CON_ENABLED)))) {
if (msm_serial_hsl_has_gsbi())
if ((ioread32(msm_hsl_port->mapped_gsbi +
GSBI_CONTROL_ADDR) & GSBI_PROTOCOL_I2C_UART)
!= GSBI_PROTOCOL_I2C_UART)
iowrite32(GSBI_PROTOCOL_I2C_UART,
msm_hsl_port->mapped_gsbi +
GSBI_CONTROL_ADDR);
if (pdata && pdata->config_gpio) {
ret = gpio_request(pdata->uart_tx_gpio,
"UART_TX_GPIO");
if (unlikely(ret)) {
pr_err("%s: gpio request failed for:%d\n",
__func__, pdata->uart_tx_gpio);
return ret;
}
ret = gpio_request(pdata->uart_rx_gpio, "UART_RX_GPIO");
if (unlikely(ret)) {
pr_err("%s: gpio request failed for:%d\n",
__func__, pdata->uart_rx_gpio);
gpio_free(pdata->uart_tx_gpio);
return ret;
}
}
}
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_get_sync(port->dev);
if (likely(port->fifosize > 12))
rfr_level = port->fifosize - 12;
else
rfr_level = port->fifosize;
spin_lock_irqsave(&port->lock, flags);
/* set automatic RFR level */
data = msm_hsl_read(port, UARTDM_MR1_ADDR);
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
data |= UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2);
data |= UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level;
msm_hsl_write(port, data, UARTDM_MR1_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
ret = request_irq(port->irq, msm_hsl_irq, IRQF_TRIGGER_HIGH,
msm_hsl_port->name, port);
if (unlikely(ret)) {
printk(KERN_ERR "%s: failed to request_irq\n", __func__);
return ret;
}
return 0;
}
static int msm_hsl_startup(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
unsigned int data, rfr_level;
int ret;
unsigned long flags;
snprintf(msm_hsl_port->name, sizeof(msm_hsl_port->name),
"msm_serial_hsl%d", port->line);
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_get_sync(port->dev);
if (likely(port->fifosize > 12))
rfr_level = port->fifosize - 12;
else
rfr_level = port->fifosize;
spin_lock_irqsave(&port->lock, flags);
/* set automatic RFR level */
data = msm_hsl_read(port, UARTDM_MR1_ADDR);
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
data |= UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2);
data |= UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level;
msm_hsl_write(port, data, UARTDM_MR1_ADDR);
/* Make sure IPR is not 0 to start with*/
msm_hsl_write(port, UARTDM_IPR_STALE_LSB_BMSK, UARTDM_IPR_ADDR);
data = 0;
if (!(is_console(port)) || (!port->cons) ||
(port->cons && (!(port->cons->flags & CON_ENABLED)))) {
msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
UARTDM_MR2_ADDR); /* 8N1 */
msm_hsl_reset(port);
data = UARTDM_CR_TX_EN_BMSK;
}
if(b_terminal_onoff == 0 && console_uart_port && (port == console_uart_port)){
msm_hsl_write(port, data, UARTDM_CR_ADDR); /* enable TX */
}else{
data |= UARTDM_CR_RX_EN_BMSK;
msm_hsl_write(port, data, UARTDM_CR_ADDR); /* enable TX & RX */
}
/* turn on RX and CTS interrupts */
msm_hsl_port->imr = UARTDM_ISR_RXSTALE_BMSK
| UARTDM_ISR_DELTA_CTS_BMSK | UARTDM_ISR_RXLEV_BMSK;
spin_unlock_irqrestore(&port->lock, flags);
ret = request_irq(port->irq, msm_hsl_irq, IRQF_TRIGGER_HIGH,
msm_hsl_port->name, port);
if (unlikely(ret)) {
printk(KERN_ERR "%s: failed to request_irq\n", __func__);
return ret;
}
spin_lock_irqsave(&port->lock, flags);
msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
return 0;
}
static int msm_hsl_startup(struct uart_port *port)
{
struct msm_hsl_port *msm_hsl_port = UART_TO_MSM(port);
struct platform_device *pdev = to_platform_device(port->dev);
struct msm_serial_hslite_platform_data *pdata = pdev->dev.platform_data;
unsigned int data, rfr_level;
int ret;
unsigned long flags;
snprintf(msm_hsl_port->name, sizeof(msm_hsl_port->name),
"msm_serial_hsl%d", port->line);
if (!(is_console(port)) || (!port->cons) ||
(port->cons && (!(port->cons->flags & CON_ENABLED)))) {
if (msm_serial_hsl_has_gsbi())
if ((ioread32(msm_hsl_port->mapped_gsbi +
GSBI_CONTROL_ADDR) & GSBI_PROTOCOL_I2C_UART)
!= GSBI_PROTOCOL_I2C_UART)
iowrite32(GSBI_PROTOCOL_I2C_UART,
msm_hsl_port->mapped_gsbi +
GSBI_CONTROL_ADDR);
if (pdata && pdata->config_gpio) {
ret = gpio_request(pdata->uart_tx_gpio,
"UART_TX_GPIO");
if (unlikely(ret)) {
pr_err("%s: gpio request failed for:%d\n",
__func__, pdata->uart_tx_gpio);
return ret;
}
ret = gpio_request(pdata->uart_rx_gpio, "UART_RX_GPIO");
if (unlikely(ret)) {
pr_err("%s: gpio request failed for:%d\n",
__func__, pdata->uart_rx_gpio);
gpio_free(pdata->uart_tx_gpio);
return ret;
}
}
}
#ifndef CONFIG_PM_RUNTIME
msm_hsl_init_clock(port);
#endif
pm_runtime_get_sync(port->dev);
if (likely(port->fifosize > 12))
rfr_level = port->fifosize - 12;
else
rfr_level = port->fifosize;
spin_lock_irqsave(&port->lock, flags);
/* set automatic RFR level */
data = msm_hsl_read(port, UARTDM_MR1_ADDR);
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK;
data &= ~UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK;
data |= UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK & (rfr_level << 2);
data |= UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK & rfr_level;
msm_hsl_write(port, data, UARTDM_MR1_ADDR);
/* Make sure IPR is not 0 to start with*/
msm_hsl_write(port, UARTDM_IPR_STALE_LSB_BMSK, UARTDM_IPR_ADDR);
data = 0;
if (!(is_console(port)) || (!port->cons) ||
(port->cons && (!(port->cons->flags & CON_ENABLED)))) {
msm_hsl_write(port, CR_PROTECTION_EN, UARTDM_CR_ADDR);
msm_hsl_write(port, UARTDM_MR2_BITS_PER_CHAR_8 | STOP_BIT_ONE,
UARTDM_MR2_ADDR); /* 8N1 */
msm_hsl_reset(port);
data = UARTDM_CR_TX_EN_BMSK;
}
data |= UARTDM_CR_RX_EN_BMSK;
msm_hsl_write(port, data, UARTDM_CR_ADDR); /* enable TX & RX */
/* turn on RX and CTS interrupts */
msm_hsl_port->imr = UARTDM_ISR_RXSTALE_BMSK
| UARTDM_ISR_DELTA_CTS_BMSK | UARTDM_ISR_RXLEV_BMSK;
spin_unlock_irqrestore(&port->lock, flags);
ret = request_irq(port->irq, msm_hsl_irq, IRQF_TRIGGER_HIGH,
msm_hsl_port->name, port);
if (unlikely(ret)) {
printk(KERN_ERR "%s: failed to request_irq\n", __func__);
return ret;
}
spin_lock_irqsave(&port->lock, flags);
msm_hsl_write(port, RESET_STALE_INT, UARTDM_CR_ADDR);
msm_hsl_write(port, 6500, UARTDM_DMRX_ADDR);
msm_hsl_write(port, STALE_EVENT_ENABLE, UARTDM_CR_ADDR);
msm_hsl_write(port, msm_hsl_port->imr, UARTDM_IMR_ADDR);
spin_unlock_irqrestore(&port->lock, flags);
return 0;
}
