static int vpe_start(void) { /* enable the frame irq, bit 0 = Display list 0 ROI done */ msm_io_w_mb(1, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET); msm_io_dump(vpe_ctrl->vpebase, 0x120); msm_io_dump(vpe_ctrl->vpebase + 0x10000, 0x250); msm_io_dump(vpe_ctrl->vpebase + 0x30000, 0x20); msm_io_dump(vpe_ctrl->vpebase + 0x50000, 0x30); msm_io_dump(vpe_ctrl->vpebase + 0x50400, 0x10); /* this triggers the operation. */ msm_io_w(1, vpe_ctrl->vpebase + VPE_DL0_START_OFFSET); wmb(); return 0; }
static int vpe_start(void) { #ifdef CONFIG_CAMERA_3D struct msm_sync *sync = (struct msm_sync *)vpe_ctrl->syncdata; #endif /* enable the frame irq, bit 0 = Display list 0 ROI done */ msm_io_w(1, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET); #ifdef CONFIG_CAMERA_3D if ((atomic_read(&sync->stereo_snap_state) == STEREO_SNAP_BUFFER1_PROCESSING) || (atomic_read(&sync->stereo_snap_state) == STEREO_SNAP_BUFFER2_PROCESSING)) #endif msm_io_dump(vpe_device->vpebase + 0x10000, 0x250); /* this triggers the operation. */ msm_io_w(1, vpe_device->vpebase + VPE_DL0_START_OFFSET); return 0; }
static int vpe_start(void) { msm_io_w_mb(1, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET); msm_io_dump(vpe_ctrl->vpebase, 0x120); msm_io_dump(vpe_ctrl->vpebase + 0x00400, 0x18); msm_io_dump(vpe_ctrl->vpebase + 0x10000, 0x250); msm_io_dump(vpe_ctrl->vpebase + 0x30000, 0x20); msm_io_dump(vpe_ctrl->vpebase + 0x50000, 0x30); msm_io_dump(vpe_ctrl->vpebase + 0x50400, 0x10); msm_io_w(1, vpe_ctrl->vpebase + VPE_DL0_START_OFFSET); wmb(); return 0; }
void msm_io_memcpy(void __iomem *dest_addr, void __iomem *src_addr, u32 len) { CDBG("%s: %p %p %d\n", __func__, dest_addr, src_addr, len); msm_io_memcpy_toio(dest_addr, src_addr, len / 4); msm_io_dump(dest_addr, len); }