int board_init(void) { u32 cpu_type = rmobile_get_cpu_type(); /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) { /* GSX: force power and clock supply */ writel(0x0000001F, SYSC_PWRONCR2); while (readl(SYSC_PWRSR2) != 0x000003E0) mdelay(20); mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); } /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); /* Configure the HSUSB block */ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); /* Choice USB0SEL */ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, HSUSB_REG_UGCTRL2_USB0SEL_EHCI); /* low power status */ setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); return 0; }
int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; /* Init PFC controller */ r8a7791_pinmux_init(); /* ETHER Enable */ gpio_request(GPIO_FN_ETH_CRS_DV, NULL); gpio_request(GPIO_FN_ETH_RX_ER, NULL); gpio_request(GPIO_FN_ETH_RXD0, NULL); gpio_request(GPIO_FN_ETH_RXD1, NULL); gpio_request(GPIO_FN_ETH_LINK, NULL); gpio_request(GPIO_FN_ETH_REFCLK, NULL); gpio_request(GPIO_FN_ETH_MDIO, NULL); gpio_request(GPIO_FN_ETH_TXD1, NULL); gpio_request(GPIO_FN_ETH_TX_EN, NULL); gpio_request(GPIO_FN_ETH_TXD0, NULL); gpio_request(GPIO_FN_ETH_MDC, NULL); gpio_request(GPIO_FN_IRQ0, NULL); mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); gpio_direction_output(GPIO_GP_5_22, 0); mdelay(20); gpio_set_value(GPIO_GP_5_22, 1); udelay(1); return 0; }
int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; /* Init PFC controller */ r8a7794_pinmux_init(); /* Ether Enable */ gpio_request(GPIO_FN_ETH_CRS_DV, NULL); gpio_request(GPIO_FN_ETH_RX_ER, NULL); gpio_request(GPIO_FN_ETH_RXD0, NULL); gpio_request(GPIO_FN_ETH_RXD1, NULL); gpio_request(GPIO_FN_ETH_LINK, NULL); gpio_request(GPIO_FN_ETH_REFCLK, NULL); gpio_request(GPIO_FN_ETH_MDIO, NULL); gpio_request(GPIO_FN_ETH_TXD1, NULL); gpio_request(GPIO_FN_ETH_TX_EN, NULL); gpio_request(GPIO_FN_ETH_MAGIC, NULL); gpio_request(GPIO_FN_ETH_TXD0, NULL); gpio_request(GPIO_FN_ETH_MDC, NULL); gpio_request(GPIO_FN_IRQ8, NULL); /* PHY reset */ mstp_clrbits_le32(PUPR3, PUPR3, PUPR3_ETH); gpio_request(GPIO_GP_1_24, NULL); mstp_clrbits_le32(PUPR1, PUPR1, PUPR1_DREQ0_N); gpio_direction_output(GPIO_GP_1_24, 0); mdelay(20); gpio_set_value(GPIO_GP_1_24, 1); udelay(1); return 0; }
int board_early_init_f(void) { /* TMU0,1 */ /* which use ? */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); /* SCIF2 */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); return 0; }
int board_early_init_f(void) { /* TMU0,1 */ /* which use ? */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) /* DVFS for reset */ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); #endif return 0; }
int board_early_init_f(void) { /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); /* SCIF0 */ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); return 0; }
int board_early_init_f(void) { /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); #if defined(CONFIG_NORFLASH) /* SCIF0 */ set_guard_reg(GPSR4, 0x34000000, 0x00000000); set_guard_reg(IPSR14, 0x00000FC7, 0x00000481); set_guard_reg(GPSR4, 0x00000000, 0x34000000); #endif mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); return 0; }
int board_early_init_f(void) { #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) /* DVFS for reset */ mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); #endif return 0; }
int board_early_init_f(void) { /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); /* SCIF0 */ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); /* SDHI */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); writel(SD_97500KHZ, SD1CKCR); writel(SD_97500KHZ, SD2CKCR); return 0; }
int board_early_init_f(void) { /* TMU */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); /* Set SD1 to the 97.5MHz */ writel(SD_97500KHZ, SD1CKCR); return 0; }
int board_early_init_f(void) { /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); /* SCIFA0 */ mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204); /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); /* SDHI0,2 */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312); /* * SD0 clock is set to 97.5MHz by default. * Set SD2 to the 97.5MHz as well. */ writel(SD2_97500KHZ, SD2CKCR); return 0; }
int board_early_init_f(void) { /* TMU */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); /* SCIF2 */ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); /* IIC1 / sh-i2c ch1 */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); #ifdef CONFIG_SH_MMCIF /* MMC */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); #endif return 0; }
int board_early_init_f(void) { mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); /* * SD0 clock is set to 97.5MHz by default. * Set SD2 to the 97.5MHz as well. */ writel(SD_97500KHZ, SD2CKCR); return 0; }
int board_early_init_f(void) { /* TMU */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); /* SCIF2 */ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); /* IIC1 / sh-i2c ch1 */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); #ifdef CONFIG_SH_MMCIF /* MMC */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); #endif #ifdef CONFIG_SH_SDHI /* SDHI1 */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312); /* * Set SD1 to the 97.5MHz */ writel(SD1_97500KHZ, SD1CKCR); #endif return 0; }
int board_early_init_f(void) { mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); /* SCIF0 */ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); /* SDHI */ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); /* * SD0 clock is set to 97.5MHz by default. * Set SD1 and SD2 to the 97.5MHz as well. */ writel(SD_97500KHZ, SD1CKCR); writel(SD_97500KHZ, SD2CKCR); return 0; }
void arch_preboot_os(void) { int i; /* stop TMU0 */ mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0); /* Stop module clock */ for (i = 0; i < ARRAY_SIZE(mstptbl); i++) { mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr, mstptbl[i].s_dis, mstptbl[i].s_ena); mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr, mstptbl[i].r_dis, mstptbl[i].r_ena); } }
int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; /* Init PFC controller */ r8a7795_pinmux_init(); /* GSX: force power and clock supply */ writel(0x0000001F, SYSC_PWRONCR2); while (readl(SYSC_PWRSR2) != 0x000003E0) mdelay(20); mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); return 0; }
int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); /* Configure the HSUSB block */ mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); /* Choice USB0SEL */ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, HSUSB_REG_UGCTRL2_USB0SEL_EHCI); /* low power status */ setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); return 0; }