static kal_uint32 charging_set_cv_voltage(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint16 register_value;
static kal_int16 pre_register_value = -1;
register_value = charging_parameter_to_value(VBAT_CV_VTH, GETARRAYNUM(VBAT_CV_VTH) ,*(kal_uint32 *)(data));
#if 0
//bq24261_set_vbreg(0x14);
bq24261_set_vbreg(register_value);
#else
//PCB workaround
if(mt6325_upmu_get_swcid() == PMIC6325_E1_CID_CODE)
{
#if defined(CV_E1_INTERNAL)
bq24261_set_vbreg(0x19);
#else
bq24261_set_vbreg(0xF);
#endif
battery_xlog_printk(BAT_LOG_CRTI,"[charging_set_cv_voltage] set low CV by 6325 E1\n");
}
else
{
if(is_mt6311_exist())
{
if(mt6311_get_chip_id()==PMIC6311_E1_CID_CODE)
{
#if defined(CV_E1_INTERNAL)
bq24261_set_vbreg(0x19);
#else
bq24261_set_vbreg(0xF);
#endif
battery_xlog_printk(BAT_LOG_CRTI,"[charging_set_cv_voltage] set low CV by 6311 E1\n");
}
else
{
if (pre_register_value != register_value) {
battery_xlog_printk(BAT_LOG_CRTI,"[charging_set_cv_voltage] disable charging\n");
bq24261_set_dis_ce(1);
}
bq24261_set_vbreg(register_value);
if (pre_register_value != register_value)
bq24261_set_dis_ce(0);
pre_register_value = register_value;
}
}
else
{
bq24261_set_vbreg(register_value);
}
}
#endif
return status;
}
static kal_uint32 charging_set_cv_voltage(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint16 register_value;
kal_uint32 cv_value = *(kal_uint32 *)(data);
kal_uint32 array_size;
kal_uint32 set_chr_cv;
array_size = GETARRAYNUM(VBAT_CV_VTH);
set_chr_cv = bmt_find_closest_level(VBAT_CV_VTH, array_size, cv_value);
register_value = charging_parameter_to_value(VBAT_CV_VTH, GETARRAYNUM(VBAT_CV_VTH), set_chr_cv);
#if 0
ncp1854_set_ctrl_vbat(register_value);
#else
//PCB workaround
if(mt6325_upmu_get_swcid() == PMIC6325_E1_CID_CODE)
{
ncp1854_set_ctrl_vbat(0x14); //3.8v
battery_xlog_printk(BAT_LOG_CRTI,"[charging_set_cv_voltage] set low CV by 6325 E1\n");
}
else
{
if(is_mt6311_exist())
{
if(mt6311_get_chip_id()==PMIC6311_E1_CID_CODE)
{
ncp1854_set_ctrl_vbat(0x14); //3.8v
battery_xlog_printk(BAT_LOG_CRTI,"[charging_set_cv_voltage] set low CV by 6311 E1\n");
}
else
{
ncp1854_set_ctrl_vbat(register_value);
}
}
else
{
ncp1854_set_ctrl_vbat(register_value);
}
}
#endif
return status;
}
static kal_uint32 charging_set_cv_voltage(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint32 array_size;
kal_uint32 set_cv_voltage;
kal_uint16 register_value;
kal_uint32 cv_value = *(kal_uint32 *)(data);
static kal_int16 pre_register_value = -1;
#if defined(HIGH_BATTERY_VOLTAGE_SUPPORT)
//highest of voltage will be 4.3V, because powerpath limitation
if(cv_value >= BATTERY_VOLT_04_300000_V)
cv_value = 4304000;
#endif
//use nearest value
if(BATTERY_VOLT_04_200000_V == cv_value)
cv_value = 4208000;
array_size = GETARRAYNUM(VBAT_CV_VTH);
set_cv_voltage = bmt_find_closest_level(VBAT_CV_VTH, array_size, cv_value);
register_value = charging_parameter_to_value(VBAT_CV_VTH, array_size, set_cv_voltage);
//PCB workaround
if(mt6325_upmu_get_swcid() == PMIC6325_E1_CID_CODE)
{
#if defined(CV_E1_INTERNAL)
bq24196_set_vreg(0x1F);//4.0v
#else
bq24196_set_vreg(0x14);//3.8v
#endif
battery_log(BAT_LOG_CRTI, "[charging_set_cv_voltage] set low CV by 6325 E1\n");
}
else
{
if(is_mt6311_exist())
{
if(mt6311_get_chip_id()==PMIC6311_E1_CID_CODE)
{
#if defined(CV_E1_INTERNAL)
bq24196_set_vreg(0x1F);//4.0v
#else
bq24196_set_vreg(0x14);//3.8v
#endif
battery_log(BAT_LOG_CRTI, "[charging_set_cv_voltage] set low CV by 6311 E1\n");
}
else
{
if (pre_register_value != register_value) {
battery_log(BAT_LOG_CRTI, "[charging_set_cv_voltage] disable charging\n");
bq24196_set_chg_config(0);
}
bq24196_set_vreg(register_value);
if (pre_register_value != register_value)
bq24196_set_chg_config(1);
pre_register_value = register_value;
}
}
else
{
bq24196_set_vreg(register_value);
}
}
return status;
}
static void pm_callback_power_off(struct kbase_device *kbdev)
{
unsigned int uiCurrentFreqCount;
volatile int polling_count = 100000;
volatile int i = 0;
struct mtk_config *config;
if (!kbdev) {
pr_alert("MALI: input parameter is NULL \n");
}
config = (struct mtk_config *)kbdev->mtk_config;
if (!config) {
pr_alert("MALI: mtk_config is NULL \n");
}
/// 1. Delay 0.01ms before power off
for (i=0; i < DELAY_LOOP_COUNT;i++);
if (DELAY_LOOP_COUNT != i)
{
pr_warn("[MALI] power off delay error!\n");
}
/// 2. Polling the MFG_DEBUG_REG for checking GPU IDLE before MTCMOS power off (0.1ms)
MFG_WRITE32(0x3, MFG_DEBUG_CTRL_REG);
do {
/// 0x13000184[2]
/// 1'b1: bus idle
/// 1'b0: bus busy
if (MFG_READ32(MFG_DEBUG_STAT_REG) & MFG_BUS_IDLE_BIT)
{
/// printk("[MALI]MFG BUS already IDLE! Ready to power off, %d\n", polling_count);
break;
}
} while (polling_count--);
if (polling_count <=0)
{
pr_warn("[MALI]!!!!MFG(GPU) subsys is still BUSY!!!!!, polling_count=%d\n", polling_count);
}
#if HARD_RESET_AT_POWER_OFF
/* Cause a GPU hard reset to test whether we have actually idled the GPU
* and that we properly reconfigure the GPU on power up.
* Usually this would be dangerous, but if the GPU is working correctly it should
* be completely safe as the GPU should not be active at this point.
* However this is disabled normally because it will most likely interfere with
* bus logging etc.
*/
//KBASE_TRACE_ADD(kbdev, CORE_GPU_HARD_RESET, NULL, NULL, 0u, 0);
kbase_os_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), GPU_COMMAND_HARD_RESET);
/// Polling the MFG_DEBUG_REG for checking GPU IDLE before MTCMOS power off (0.1ms)
MFG_WRITE32(0x3, MFG_DEBUG_CTRL_REG);
do {
/// 0x13000184[2]
/// 1'b1: bus idle
/// 1'b0: bus busy
if (MFG_READ32(MFG_DEBUG_STAT_REG) & MFG_BUS_IDLE_BIT)
{
/// printk("[MALI]MFG BUS already IDLE! Ready to power off, %d\n", polling_count);
break;
}
} while (polling_count--);
if (polling_count <=0)
{
printk("[MALI]!!!!MFG(GPU) subsys is still BUSY!!!!!, polling_count=%d\n", polling_count);
}
g_power_off_gpu_freq_idx = mt_gpufreq_get_cur_freq_index(); // record current freq. index.
//printk("MALI: GPU power off freq idx : %d\n",g_power_off_gpu_freq_idx );
#if 1
uiCurrentFreqCount = mt_gpufreq_get_dvfs_table_num(); // get freq. table size
mt_gpufreq_target(uiCurrentFreqCount-1); // set gpu to lowest freq.
#endif
/* MTK clock modified */
#ifdef CONFIG_MTK_CLKMGR
disable_clock( MT_CG_MFG_BG3D, "GPU");
disable_clock( MT_CG_DISP0_SMI_COMMON, "GPU");
#endif
if(mt6325_upmu_get_swcid() >= PMIC6325_E3_CID_CODE)
{
mt_gpufreq_voltage_enable_set(0);
}
#ifdef ENABLE_COMMON_DVFS
ged_dvfs_gpu_clock_switch_notify(0);
#endif
mtk_set_vgpu_power_on_flag(MTK_VGPU_POWER_OFF); // the power status is "power off".
#endif
}
