static int _hsmci_shutdown (SIM_HBA *hba) { CONFIG_INFO *cfg; SIM_MMC_EXT *ext; hsmci_ext_t *hsmci; uintptr_t base; ext = (SIM_MMC_EXT *)hba->ext; cfg = (CONFIG_INFO *)&hba->cfg; hsmci = (hsmci_ext_t *)ext->handle; base = hsmci->base; /* Reset and disable controller */ WRITE32 (MCI_CR, SWRST|PWSDIS); delay (100); WRITE32 (MCI_CR, MCIDIS | PWSDIS); /* Indicate we are done with DMA lib */ dmac_fini(hsmci->dmac_dev); munmap_device_memory ((void *)pioa_pdsr, 4); munmap_device_memory ((void *)hsmci->base, cfg->MemLength[0]); munmap_device_io (hsmci->pio_base, AT91SAM9G45_PIO_SIZE); munmap_device_io (hsmci->pmc_base, PMC_SIZE); free(hsmci); return (MMC_SUCCESS); }
_X_EXPORT int xf86ReadBIOS(unsigned long Base, unsigned long Offset, unsigned char *Buf, int Len) { unsigned char *ptr; int psize; int mlen; psize = xf86getpagesize(); Offset += Base & (psize - 1); Base &= ~(psize - 1); mlen = (Offset + Len + psize - 1) & ~(psize - 1); ptr = (unsigned char *)mmap_device_memory((caddr_t)0, mlen, PROT_READ, 0, (off_t)Base); if ((long)ptr == -1) { xf86Msg(X_WARNING, "xf86ReadBIOS: %s mmap[s=%x,a=%lx,o=%lx] failed (%s)\n", DEV_MEM, Len, Base, Offset, strerror(errno)); return(-1); } #ifdef DEBUG ErrorF("xf86ReadBIOS: BIOS at 0x%08x has signature 0x%04x\n", Base, ptr[0] | (ptr[1] << 8)); #endif (void)memcpy(Buf, (void *)(ptr + Offset), Len); (void)munmap_device_memory((caddr_t)ptr, mlen); #ifdef DEBUG xf86MsgVerb(X_INFO, 3, "xf86ReadBIOS(%x, %x, Buf, %x)" "-> %02x %02x %02x %02x...\n", Base, Offset, Len, Buf[0], Buf[1], Buf[2], Buf[3]); #endif return(Len); }
void omap3_dinit(void *hdl) { omap3_spi_t *dev = hdl; /* * unmap the register, detach the interrupt */ InterruptDetach(dev->iid_spi); munmap_device_io(dev->vbase, OMAP3_SPI_REGLEN); /* * Disable EDMA */ if (dev->edma) { omap3_edma_disablespi(dev); InterruptDetach(dev->iid_edma); omap3_edma_detach (dev); munmap_device_memory((void *)dev->edmavbase, DM6446_EDMA_SIZE); munmap(dev->dmabuf, OMAP3_SPI_MAXDMALEN); ConnectDetach(dev->edma_coid); } ConnectDetach(dev->coid); ChannelDestroy(dev->chid); free(hdl); }
int _close_PCI(int pci_handle, int BASE0, int BASE1){ int temp; #ifdef __QNX__ pci_detach(pci_handle); temp=munmap_device_memory((unsigned int *)BASE0, 256); if (temp==-1){ perror("munmap_device_memory failed"); return -1; } temp=munmap_device_memory((unsigned int *)BASE1, 524288); if (temp==-1){ perror("munmap_device_memory failed"); return -1; } #endif return 1; }
int32_t omap3530_sdma_attach(omap3530_spi_t *omap3530) { int tx_idx = omap3530->sdma_tx_chid = -1; int rx_idx = omap3530->sdma_rx_chid = -1; rsrc_request_t req = { 0 }; /* Map in DMA registers */ if ((omap3530->dma4 = mmap_device_memory (0, sizeof (dma4_t), PROT_READ | PROT_WRITE | PROT_NOCACHE, 0, DMA4_BASE_ADDR)) == MAP_FAILED) { fprintf(stderr, "Unable to mmap DMA (%s) \n", strerror (errno)); return (-1); } /* *********** SPI: transmit **************** */ req.length = 1; req.flags = RSRCDBMGR_DMA_CHANNEL; if (rsrcdbmgr_attach (&req, 1) == -1) { fprintf(stderr, "Unable to aquire DMA channels (%s) \n", strerror (errno)); munmap_device_memory (omap3530->dma4, sizeof (dma4_t)); return (-1); } tx_idx = omap3530->sdma_tx_chid = req.start; /* *********** SPI: receive **************** */ memset (&req, 0, sizeof (req)); req.length = 1; req.flags = RSRCDBMGR_DMA_CHANNEL; if (rsrcdbmgr_attach (&req, 1) == -1) { fprintf(stderr, "Unable to aquire DMA channels (%s) \n", strerror (errno)); omap3530_sdma_detach (omap3530); return (-1); } rx_idx = omap3530->sdma_rx_chid = req.start; // do some common initiailization omap3530->dma4->channel[tx_idx].cse = 1; omap3530->dma4->channel[tx_idx].cde = 1; omap3530->dma4->channel[rx_idx].cse = 1; omap3530->dma4->channel[rx_idx].cde = 1; omap3530->dma4->channel[tx_idx].cdf = 0; omap3530->dma4->channel[rx_idx].csf = 0; omap3530->dma4->channel[tx_idx].csdp = DMA4_CSDP_DATA_TYPE_8BIT; omap3530->dma4->channel[rx_idx].csdp = DMA4_CSDP_DATA_TYPE_8BIT; return 0; }
int GPIORelaisController::closeMap() { int res = 0; info_printf("GPIORelaisController::closeMap()\n"); // if (munmap_device_memory( gpioPortBase, gpioPortLen ) == -1 ) { ??? if (munmap_device_memory( gpioregs, gpioPortLen ) == -1 ) { info_printf("GPIORelaisController::closeMap: munmap_device_memory failed \n"); } /* if ( munmap(gpioregs, mapLen) < 0) { printf("munmap() error"); res = 1; } // printf("gioregs unmapped\n"); close(memfd); */ return res; }
static void dmac_fini (dmac_dev_t * dmac_dev) { rsrc_request_t req; int timeout = 0; munmap (dmac_dev->lli, (MAX_LLI_NUM) * sizeof(at91sam9xx_dmac_bd_t) ); /* Disable channel */ dmac_dev->dmac->chdr |= (1 << dmac_dev->chid); while (dmac_dev->dmac->chsr & (1 <<dmac_dev->chid)) { delay (1); if (timeout++ > TIMEOUT_LOOPS) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "%s: release DMAC channel time out\n", __func__); break; } } /* release DMAC mmap resources */ munmap (dmac_dev->lli, (MAX_LLI_NUM) * sizeof(at91sam9xx_dmac_bd_t) ); /* Release DMAC channel */ memset(&req, 0, sizeof(req)); req.length = 1; req.flags = RSRCDBMGR_DMA_CHANNEL; req.start = dmac_dev->chid; req.end = dmac_dev->chid; /* Return the resource to the database: */ rsrcdbmgr_detach( &req, 1); if (dmac_dev != NULL) { if ( dmac_dev->dmac!= MAP_FAILED) munmap_device_memory((void *)dmac_dev->dmac, sizeof(at91sam9xx_dmac_t)); free (dmac_dev); } }
void omap3530_sdma_detach(omap3530_spi_t *omap3530) { rsrc_request_t req = { 0 }; if (omap3530->sdma_tx_chid != -1) { req.length = 1; req.start = omap3530->sdma_tx_chid; req.flags = RSRCDBMGR_DMA_CHANNEL; rsrcdbmgr_detach (&req, 1); } if (omap3530->sdma_rx_chid != -1) { memset (&req, 0, sizeof (req)); req.length = 1; req.start = omap3530->sdma_rx_chid; req.flags = RSRCDBMGR_DMA_CHANNEL; rsrcdbmgr_detach (&req, 1); } munmap_device_memory (omap3530->dma4, sizeof (dma4_t)); }
static void unmapVidMem(int ScreenNum, pointer Base, unsigned long Size) { munmap_device_memory((caddr_t)Base, Size); }
void *omap3_init(void *hdl, char *options) { omap3_spi_t *dev; uintptr_t base; int i; uint32_t reg; dev = calloc(1, sizeof(omap3_spi_t)); if (dev == NULL) return NULL; //Set defaults dev->pbase = OMAP3_SPI1_BASE; dev->irq_spi = OMAP3_SPI_SPI1_INTR; dev->clock = OMAP3_SPI_INPUT_CLOCK; dev->channel_num = 1; dev->force = 0; dev->edmapbase = DM816x_EDMA_BASE; dev->irq_edma = 0; /* We use interrupt of receive channel */ dev->edma = 0; dev->num_cs = 1; dev->cs_delay = 0; dev->edma_tx_chid = dev->edma_rx_chid = -1; if (omap3_options(dev, options)) goto fail0; /* * Map in SPI registers */ if ((base = mmap_device_io(OMAP3_SPI_REGLEN, dev->pbase)) == (uintptr_t)MAP_FAILED) goto fail0; dev->vbase = base; /* Reset the SPI interface * and wait for the reset to complete */ set_port(base + OMAP3_MCSPI_SYS_CONFIG, OMAP3_MCSPI_CONFIG_SOFT_RESET, OMAP3_MCSPI_CONFIG_SOFT_RESET); while ( !(in32(base + OMAP3_MCSPI_SYS_CONFIG) & 1)) { nanospin_ns(20); } /*Set Master mode -- single channel mode*/ out32((base + OMAP3_MCSPI_MODCTRL_OFFSET), (in32(base + OMAP3_MCSPI_MODCTRL_OFFSET) & OMAP3_MCSPI_MODCTRL_MASTER_SEL)|OMAP3_MCSPI_MODCTRL_MULTI_CH_SEL); /* * Calculate all device configuration here */ for (i = 0; i < dev->num_cs; i++){ //we have just one device defined in the driver till now.... devctrl[i] = omap3_cfg(dev, &devlist[i].cfg); if(dev->force){ /* if we need to set the default CSx level to other than defaul low, we need to kick it*/ out32((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14 * i), devctrl[i]|SPI_COMM_TX_RX <<12); set_port(base + OMAP3_MCSPI_CH1_CTRL_OFFSET+0x14*i, OMAP3_MCSPI_CHANNEL_ENABLE, OMAP3_MCSPI_CHANNEL_ENABLE); /* force CS */ set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*i),OMAP3_MCSPI_FORCE_MODE_ONE, OMAP3_MCSPI_FORCE_MODE_ONE); delay(1); /*un force CS */ set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*i),OMAP3_MCSPI_FORCE_MODE_ONE, 0); set_port(base + OMAP3_MCSPI_CH1_CTRL_OFFSET+0x14*i, OMAP3_MCSPI_CHANNEL_ENABLE, 0); } } /* * Attach SPI interrupt */ if (omap3_attach_intr(dev)) goto fail1; dev->spi.hdl = hdl; /* Clear the appropriate Interrupts if any*/ reg= in32(base + OMAP3_MCSPI_IRQ_STATUS_OFFSET) ; out32((base + OMAP3_MCSPI_IRQ_STATUS_OFFSET), reg); if (dev->edma) { if (omap3_init_edma(dev)) dev->edma=0; /* * Attach SDMA interrupt */ if (omap3_edma_attach_intr(dev)){ printf("%s(%d): omap3_edma_attach_intr failed\n", __func__, __LINE__); goto fail2; } } return dev; fail2: munmap_device_memory ((void *)dev->edmavbase, DM6446_EDMA_SIZE); fail1: munmap_device_io(dev->vbase, OMAP3_SPI_REGLEN); fail0: free(dev); return NULL; }
int hsmci_init (SIM_HBA *hba) { CONFIG_INFO *cfg; SIM_MMC_EXT *ext; hsmci_ext_t *hsmci = NULL; uintptr_t base; ext = (SIM_MMC_EXT *)hba->ext; cfg = (CONFIG_INFO *)&hba->cfg; hba->verbosity = 4; if (!ext->opts) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: missing board-specific options\n"); goto ARGSERR; } if ((hsmci = calloc(1, sizeof(hsmci_ext_t))) == NULL) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: alloc memory failed\n"); goto ERR; } cfg->MemLength[0] = 0x1000; cfg->NumMemWindows = 1; cfg->MemBase[0] = cfg->IOPort_Base[0]; base = (uintptr_t)mmap_device_memory(NULL, cfg->MemLength[0], PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, cfg->MemBase[0]); if (base == (uintptr_t)MAP_FAILED) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_memory failed\n"); goto ERR; } hsmci->clock = 133000000; hsmci->base = base; hsmci->hba = hba; ext->handle = hsmci; ext->clock = hsmci->clock; ext->detect = _hsmci_detect; ext->powerup = _hsmci_powerup; ext->powerdown = _hsmci_powerdown; ext->cfg_bus = _hsmci_cfg_bus; ext->set_clock = _hsmci_clock; ext->set_blksz = _hsmci_block_size; ext->interrupt = _hsmci_interrupt; ext->command = _hsmci_command; ext->setup_dma = _hsmci_setup_dma; ext->dma_done = _hsmci_dma_done; ext->setup_pio = _hsmci_setup_pio; ext->pio_done = _hsmci_pio_done; ext->shutdown = _hsmci_shutdown; /* Parse options */ hsmci->port = -1; hsmci->blksz = BLK_LENGTH; hsmci->slot = 0; /* Hardcode DMAC controller base address according to G45 datasheet * since this driver is specifically for G45 SoC */ hsmci->dbase = DMAC_BASE; if (!ext->opts) goto ARGSERR; if (hsmci_args(hba, ext->opts) == -1) goto ARGSERR; /* * Set Src/Dst Request peripheral identifier SRC_PER/DST_PER * handshaking interface # according to Table 41-1 DMA Channel Definition * According to datasheet Table 35-2, the I/O line of mci0_da0 is pa2. * According to datasheet Table 35-2, the I/O line of mci1_da0 is pa23. */ if (hsmci->port == 0) { hsmci->dintf = 0; hsmci->da0_mask = (1<<2); } else { hsmci->dintf=13; hsmci->da0_mask = (1<<23); } /* Map G45 PIOA for polling busy signal */ pioa_pdsr = (uint32_t *)mmap_device_memory(NULL, 4, PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, PIOA_PDSR); if (pioa_pdsr == (uint32_t *)MAP_FAILED) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_memory failed\n"); goto ERR; } if ( (uintptr_t) MAP_FAILED == ( hsmci->pio_base = mmap_device_io( AT91SAM9G45_PIO_SIZE, AT91SAM9G45_PIOD_BASE ) ) ) { slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_io for PIOD_PDSR failed" ); goto ERR; } /* Configure CD and WP PIO */ InterruptDisable(); #define CFG_PIO(reg) out32( hsmci->pio_base + (reg), AT91SAM9G45_MCI_PIO_BITS ) CFG_PIO( AT91SAM9G45_PIO_PER ); /* Ensable PIO */ CFG_PIO( AT91SAM9G45_PIO_ODR ); /* Disable output */ CFG_PIO( AT91SAM9G45_PIO_IFDR ); /* Disable glitch input filter */ CFG_PIO( AT91SAM9G45_PIO_CODR ); /* Clear output data */ CFG_PIO( AT91SAM9G45_PIO_IDR ); /* Disable interrupt */ CFG_PIO( AT91SAM9G45_PIO_MDDR ); /* Disable multi-driver */ CFG_PIO( AT91SAM9G45_PIO_PUER ); /* Enable pull-up */ CFG_PIO( AT91SAM9G45_PIO_OWDR ); /* Output write disable */ #undef CFG_PIO InterruptEnable(); /* Configure capacity of controller */ ext->hccap |= MMC_HCCAP_BW1 | MMC_HCCAP_BW4 | MMC_HCCAP_DMA | MMC_HCCAP_BW8 | MMC_HCCAP_HS; // Use the flag MMC_HCCAP_NOCD_BUSY to inform the MMCSD stack that this hardware has R1B bug // ext->hccap |= MMC_HCCAP_BW1 | MMC_HCCAP_BW4 | MMC_HCCAP_DMA | MMC_HCCAP_BW8 | MMC_HCCAP_HS | MMC_HCCAP_NOCD_BUSY; /* Disable the controller and soft reset */ WRITE32(MCI_CR, SWRST | PWSDIS); delay (100); WRITE32(MCI_CR, MCIDIS | PWSDIS); /* Disable DMA */ WRITE32(MCI_DMA, (READ32(MCI_DMA) & (~(DMAEN)))); /* Enable the controller */ WRITE32(MCI_CR, MCIEN | PWSDIS); WRITE32(MCI_IDR, 0xffffffff); /* Set Timeout to Max */ WRITE32(MCI_DTOR, 0x7f); /* Use the lowest baudrate */ WRITE32 (MCI_MR, 0xff | WRPROOF| RDPROOF); hsmci->dmac_dev = dmac_init(hsmci); if (hsmci->dmac_dev == NULL) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: dmafuncs init FAILED\n"); goto ERR; } hsmci->dmac_dev->io_addr = cfg->MemBase[0] + MCI_FIFO; hsmci->dmac_dev->blksz = hsmci->blksz; /* Select slot, set bus to 1 bit */ WRITE32 (MCI_SDCR, hsmci->slot); if (!cfg->Description[0]) strncpy(cfg->Description, "Atmel HSMCI ", sizeof(cfg->Description)); if ( (uintptr_t) MAP_FAILED == ( hsmci->pmc_base = mmap_device_io(PMC_SIZE, PMC_BASE) ) ) { slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_io for PMC failed" ); goto ERR; } return (MMC_SUCCESS); ARGSERR: printf("\nImproper board-specific options used. Accepting args: \n"); printf(" port=# The MCI port been used (0 or 1)\n"); printf("NOTE:\n"); printf(" 1. The args are seperated by colon ':'\n"); printf("Example:\n"); printf("at91sam9g45 port 0: devb-mmcsd-at91sam9g45 mmcsd ioport=0xFFF80000,irq=11,bs=port=0\n"); printf("at91sam9g45 port 1: devb-mmcsd-at91sam9g45 mmcsd ioport=0xFFFD0000,irq=29,bs=port=1\n"); ERR: if (hsmci) { munmap_device_memory ((void *)hsmci->base, (uint32_t)cfg->MemLength[0]); if (hsmci->pio_base) munmap_device_io (hsmci->pio_base, AT91SAM9G45_PIO_SIZE); free (hsmci); } if (pioa_pdsr != (uint32_t *)MAP_FAILED) munmap_device_memory ((void *)pioa_pdsr, 4); return (MMC_FAILURE); }
/****************************** * DMAC functions START *****************************/ static dmac_dev_t * dmac_init (hsmci_ext_t *hsmci) { rsrc_request_t req; dmac_dev_t *dmac_dev; int timeout; /* Allocated memory for channel */ dmac_dev = (dmac_dev_t*)calloc(1, sizeof (dmac_dev_t)); if (dmac_dev == NULL) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: DMAC calloc failed\n"); return NULL; } /* Map DMAC controller */ dmac_dev->dmac = (at91sam9xx_dmac_t *)mmap_device_memory(NULL,0x200, PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, (uint32_t)(hsmci->dbase)); if (dmac_dev->dmac == MAP_FAILED) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: DMAC MAP_FAILED\n"); free (dmac_dev); return NULL; } /* Apply DMAC channel */ memset(&req, 0, sizeof(req)); req.length = 1; req.flags = RSRCDBMGR_DMA_CHANNEL; if (rsrcdbmgr_attach( &req, 1) == -1) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: Cannot acquire DMAC channel\n"); munmap_device_memory((void *)dmac_dev->dmac, sizeof(at91sam9xx_dmac_t)); free (dmac_dev); return NULL; } else { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: Use DMAC channel %lld\n", req.start); dmac_dev->chid = req.start; } /* Stop channel in case it is running */ dmac_dev->dmac->chdr = 1 << (dmac_dev->chid); timeout = 0; while (dmac_dev->dmac->chsr & (1 <<dmac_dev->chid)) { delay (1); if (timeout++ > 2000) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "%s: release DMAC channel time out\n", __func__); break; } } /* Reset HW LLI table*/ memset(&(dmac_dev->dmac->lli[dmac_dev->chid]), 0, sizeof(at91sam9xx_dmac_lli_t)); /* Alloc buffer link list memory */ dmac_dev->lli = mmap (0, (MAX_LLI_NUM) * sizeof(at91sam9xx_dmac_bd_t), PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, NOFD, 0); if (dmac_dev->lli == MAP_FAILED) { slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: DMA setup_xfer map failed\n"); return NULL; } /* Initilize the link list */ memset(dmac_dev->lli, 0, MAX_LLI_NUM * sizeof(at91sam9xx_dmac_bd_t)); /* Get link list physical address here and assign them in setup_xfer to save CPU time */ lli_mphy = (uint32_t) mphys(&dmac_dev->lli[0]); lli_size = sizeof(at91sam9xx_dmac_bd_t); /* * Associate Channel chid Src/Dst Request peripheral identifier * SRC_PER/DST_PER handshaking interface */ dmac_dev->dmac->lli[dmac_dev->chid].cfg = DMAC_SOD_DISABLE | (hsmci->dintf << 0) | (hsmci->dintf << 4); dmac_dev->dmac->en = DMAC_ENABLE; return dmac_dev; }