void __init
ev64360_setup_peripherals(void)
{
u32 base;
/* Set up window for boot CS */
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
/* We only use the 32-bit flash */
mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
&ev64360_flash_size_0);
ev64360_flash_size_1 = 0;
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
TODC_INIT(TODC_TYPE_DS1501, 0, 0,
ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
/* Set up Enet->SRAM window */
mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
/* Give enet r/w access to memory region */
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
#if defined(CONFIG_NOT_COHERENT_CACHE)
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
#else
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
/*
* Setting the SRAM to 0. Note that this generates parity errors on
* internal data path in SRAM since it's first time accessing it
* while after reset it's not configured.
*/
memset(sram_base, 0, MV64360_SRAM_SIZE);
/* set up PCI interrupt controller */
ev64360_intr_setup();
}
void __init
katana_setup_peripherals(void)
{
u32 base;
/* Set up windows for boot CS, soldered & socketed flash, and CPLD */
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
/* Assume firmware set up window sizes correctly for dev 0 & 1 */
mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base,
&katana_flash_size_0);
if (katana_flash_size_0 > 0) {
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
}
mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base,
&katana_flash_size_1);
if (katana_flash_size_1 > 0) {
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
(KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0),
katana_flash_size_1, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
}
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
/* Set up Enet->SRAM window */
mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
/* Give enet r/w access to memory region */
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
/* Must wait until window set up before retrieving board id */
katana_get_board_id();
/* Enumerate pci bus (must know board id before getting proc number) */
if (katana_get_proc_num() == 0)
bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
#if defined(CONFIG_NOT_COHERENT_CACHE)
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
#else
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
/*
* Setting the SRAM to 0. Note that this generates parity errors on
* internal data path in SRAM since it's first time accessing it
* while after reset it's not configured.
*/
memset(sram_base, 0, MV64360_SRAM_SIZE);
/* Only processor zero [on 3750] is an PCI interrupt controller */
if (katana_get_proc_num() == 0)
katana_intr_setup();
}
