/*******************************************************************************
**
** onuPonPatternBurstTransmit
** ____________________________________________________________________________
**
** DESCRIPTION: The function turn on or off actuacl burst transmission
**
** PARAMETERS: when on == true transmission is on
** when off == false transmission is off
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuPonPatternBurstTransmit(MV_BOOL on)
{
MV_STATUS status;
MV_U32 gpioGroup, gpioMask;
MV_U32 trans_value = 0;
if (mvCtrlRevGet() == ONU_ASIC_REV_Z2) {
/* ASIC Rev Z2 */
/* =========== */
PON_GPIO_GET(BOARD_GPP_PON_XVR_TX, gpioGroup, gpioMask);
if (gpioMask == PON_GPIO_NOT_USED)
return(MV_ERROR);
trans_value = (on == MV_TRUE ? ~gpioMask /*0*/: gpioMask /*1*/);
status = mvGppTypeSet(gpioGroup, gpioMask, trans_value);
if (status != MV_OK)
return(MV_ERROR);
} else if (mvCtrlRevGet() == ONU_ASIC_REV_A0) {
/* ASIC Rev A0 */
/* =========== */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_IO_EN, ONU_PHY_OUTPUT, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl enable - output\n\r");
return(MV_ERROR);
}
}
transmit_up = on;
return(MV_OK);
}
/*******************************************************************************
**
** onuPonTxPowerControlInit
** ____________________________________________________________________________
**
** DESCRIPTION: The function initialyzes TX power control pins
**
** PARAMETERS: None
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuPonTxPowerControlInit(void)
{
MV_U32 gpioPinNum, gpioGroup, gpioMask;
MV_U32 regVal, mppGroup;
MV_GPP_HAL_DATA halData;
MV_U32 devId = mvCtrlModelGet();
MV_STATUS status = MV_OK;
gpioPinNum = mvBoarGpioPinNumGet(BOARD_GPP_PON_XVR_TX_POWER, 0);
if (gpioPinNum != MV_ERROR) {
mppGroup = mvCtrlMppRegGet(gpioPinNum / 8);
/* Set TX power MPP to GPP mode */
regVal = MV_REG_READ(mppGroup);
regVal &= ~(0xf << ((gpioPinNum % 8) * 4));
MV_REG_WRITE(mppGroup, regVal);
halData.ctrlRev = mvCtrlRevGet();
status = mvGppInit(&halData);
if (status == MV_OK) {
/* Set TX power GPP pin direction to OUT */
gpioGroup = gpioPinNum / 32;
gpioMask = 1 << gpioPinNum;
status = mvGppTypeSet(gpioGroup, gpioMask, (MV_GPP_OUT & gpioMask));
}
} else if (devId == MV_6601_DEV_ID)
status = MV_ERROR;
return(status);
}
/********************************************************************
* soc_type_read -
*********************************************************************/
int soc_type_read(char *buffer, char **buffer_location, off_t offset, int buffer_length, int *zero, void *ptr)
{
int count = 0;
char tmp_buffer[1000] = { 0 };
#ifdef CONFIG_ARCH_FEROCEON_MV78XX0
char name[100] = { 0 };
#endif /* */
if (offset > 0)
return 0;
#ifdef CONFIG_ARCH_FEROCEON_MV78XX0
mvCtrlModelRevNameGet(name);
count += sprintf(tmp_buffer, "%s\n", name);
#endif /* */
#ifdef CONFIG_MV88F6281
count += sprintf(tmp_buffer, "%s%x Rev %d\n", SOC_NAME_PREFIX, mvCtrlModelGet(), mvCtrlRevGet());
#endif /* */
count += mvCpuIfPrintSystemConfig(tmp_buffer, count);
*(tmp_buffer + count) = '\0';
sprintf(buffer, "%s", tmp_buffer);
return count;
}
MV_STATUS my_mvSysCesaInit(int numOfSession, int queueDepth, void *osHandle)
{
MV_CESA_HAL_DATA halData;
MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1];
MV_STATUS status;
MV_U8 chan;
status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1);
if (status == MV_OK) {
for (chan = 0; chan < MV_CESA_CHANNELS; chan++) {
status = mvCesaTdmaWinInit(chan, addrWinMap);
if (status != MV_OK) {
mvOsPrintf("Error, unable to initialize CESA windows for channel(%d)\n", chan);
break;
}
halData.sramPhysBase[chan] = (MV_ULONG)mv_crypto_virt_base_get(chan);
halData.sramVirtBase[chan] = (MV_U8 *)mv_crypto_virt_base_get(chan);
halData.sramOffset[chan] = 0;
}
if (status == MV_OK) {
halData.ctrlModel = mvCtrlModelGet();
halData.ctrlRev = mvCtrlRevGet();
status = mvCesaHalInit(numOfSession, queueDepth,
osHandle, &halData);
}
}
return status;
}
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FLASH_CFI_DRIVER
int portwidth;
MV_U32 devParam;
#endif
#if defined(MV_INCLUDE_TWSI)
MV_TWSI_ADDR slave;
#endif
MV_GPP_HAL_DATA gppHalData;
unsigned int i;
maskAllInt();
/* must initialize the int in order for udelay to work */
//alior interrupt_init();
timer_init();
/* Init the Board environment module (device bank params init) */
mvBoardEnvInit();
#if defined(MV_INCLUDE_TWSI)
slave.type = ADDR7_BIT;
slave.address = 0;
mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0);
#endif
/* Init the Controlloer environment module (MPP init) */
mvCtrlEnvInit();
mvBoardDebugLed(3);
/* Init the Controller CPU interface */
mvCpuIfInit(mvCpuAddrWinMap);
/* Init the GPIO sub-system */
gppHalData.ctrlRev = mvCtrlRevGet();
mvGppInit(&gppHalData);
/* arch number of Integrator Board */
gd->bd->bi_arch_number = 529; //KW2 arch number
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
/* relocate the exception vectors */
/* U-Boot is running from DRAM at this stage */
for(i = 0; i < 0x100; i+=4)
{
*(unsigned int *)(0x0 + i) = *(unsigned int*)(TEXT_BASE + i);
}
mvBoardDebugLed(4);
return 0;
}
/*******************************************************************************
* mvSysCntmrInit - Initialize the Cntmr subsystem
*
* DESCRIPTION:
*
* INPUT:
* None
* OUTPUT:
* None
* RETURN:
* None
*
*******************************************************************************/
MV_STATUS mvSysCntmrInit(void)
{
MV_CNTMR_HAL_DATA halData;
halData.ctrlModel = mvCtrlModelGet();
halData.ctrlRev = mvCtrlRevGet();
halData.ctrlFamily=mvCtrlDevFamilyIdGet(halData.ctrlModel);
return mvCntmrHalInit(&halData);
}
int board_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
if (whoAmI() != 0)
return 0;
#if defined(MV_INCLUDE_TWSI)
MV_TWSI_ADDR slave;
#endif
unsigned int i;
maskAllInt();
/* Init the Board environment module (device bank params init) */
mvBoardEnvInit();
#if defined(MV_INCLUDE_TWSI)
slave.type = ADDR7_BIT;
slave.address = 0;
mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0);
#endif
/* Init the Controlloer environment module (MPP init) */
mvCtrlEnvInit();
#if defined(CONFIG_DISPLAY_CPUINFO)
late_print_cpuinfo(); /* display cpu info (and speed) */
#endif
mvBoardDebugLed(2);
mvCpuIfInit(mvCpuAddrWinMap);
#ifdef MV_NOR_BOOT
env_init();
#endif
/* Init the GPIO sub-system */
MV_GPP_HAL_DATA gppHalData;
gppHalData.ctrlRev = mvCtrlRevGet();
mvGppInit(&gppHalData);
gd->bd->bi_arch_number = 528;
gd->bd->bi_boot_params = 0x00000100;
/* relocate the exception vectors */
/* U-Boot is running from DRAM at this stage */
for (i = 0; i < 0x100; i += 4)
*(unsigned int*)(0x0 + i) =
*(unsigned int*)(CONFIG_SYS_TEXT_BASE + i);
mvBoardDebugLed(4);
return 0;
}
MV_STATUS mvGeneralInit(void)
{
/* Check is its A370 A0 */
if (mvCtrlRevGet() == 0)
sramConfig(); /* Armada 370 - Must Run the sram reconfig WA */
#if !defined(MV_NO_PRINT)
mvUartConfig(); /* prepare UART configuration (MPP's & interface selection) */
mvUartInit();
DEBUG_INIT_S("\n\nGeneral initialization - Version: " GENERAL_VERION "\n");
#endif
return MV_OK;
}
static void mvEthComplexGbeClockControlSet(void)
{
MV_U32 reg;
/* Thus fields are not exists in ZX revision */
if (mvCtrlRevGet() <= MV_88F6720_Z3_ID)
return;
/* Change default value of Bit 23, and 28 to NegEdge(0) */
reg = MV_REG_READ(MV_ETHCOMP_GBE_PHY_CLOCK_CTRL_REG);
/* Field - Switch Port4 To MPP Data Sample */
reg &= ~(ETHCC_GBE_PHY_P4_SW_TO_MPP_EDGE_MASK);
/* Field - GbE Port 0 To MPP Data Sample */
reg &= ~(ETHCC_GBE_PHY_GBE_P0_TO_MPP_EDGE_MASK);
MV_REG_WRITE(MV_ETHCOMP_GBE_PHY_CLOCK_CTRL_REG, reg);
}
/*******************************************************************************
* mvSysUsbHalInit - Initialize the USB subsystem
*
* DESCRIPTION:
*
* INPUT:
* None
* OUTPUT:
* None
* RETURN:
* None
*
*******************************************************************************/
MV_STATUS mvSysUsbInit(MV_U32 dev, MV_BOOL isHost)
{
MV_USB_HAL_DATA halData;
MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1];
MV_STATUS status;
status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1);
if(status == MV_OK)
status = mvUsbWinInit(dev, addrWinMap);
if(status == MV_OK) {
halData.ctrlModel = mvCtrlModelGet();
halData.ctrlRev = mvCtrlRevGet();
status = mvUsbHalInit(dev, isHost, &halData);
}
return status;
}
void mvEthComplexGphyPortSmiSrcSet(MV_U32 phy, MV_U32 src)
{
MV_U32 reg;
/* In A0 added Phy Smi source configuration for ports 0 and 3.
** In Zx, only Phy Smi source for 1,2 are configurable, but no
** need to modify the default values. */
if (mvCtrlRevGet() <= MV_88F6720_Z3_ID)
return;
reg = MV_REG_READ(MV_ETHCOMP_CTRL_REG);
reg &= ~ETHCC_GBE_PHY_PORT_SMI_SRC_MASK(phy);
src <<= ETHCC_GBE_PHY_PORT_SMI_SRC_OFFSET(phy);
src &= ETHCC_GBE_PHY_PORT_SMI_SRC_MASK(phy);
reg |= src;
MV_REG_WRITE(MV_ETHCOMP_CTRL_REG, reg);
}
/*******************************************************************************
* mvGppTypeSet - Enable a GPP (OUT) pin
*
* DESCRIPTION:
*
* INPUT:
* group - GPP group number
* mask - 32bit mask value. Each set bit in the mask means that the type
* of corresponding GPP will be set. Other GPPs are ignored.
* value - 32bit value that describes GPP type per pin.
*
* OUTPUT:
* None.
*
* EXAMPLE:
* Set GPP8 to input and GPP15 to output.
* mvGppTypeSet(0, (GPP8 | GPP15),
* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) );
*
* RETURN:
* None.
*
*******************************************************************************/
MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value)
{
if (group >= MV_GPP_MAX_GROUP)
{
DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n"));
return MV_BAD_PARAM;
}
gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value);
/* Workaround for Erratum FE-MISC-70*/
if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1))
{
mask &= 0x2;
gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value);
} /*End of WA*/
return MV_OK;
}
MV_VOID mvBoardEnvInit(MV_VOID)
{
MV_U32 boardId= mvBoardIdGet();
if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
{
mvOsPrintf("mvBoardEnvInit:Board unknown.\n");
return;
}
if (mvBoardIdGet() != XCAT98DX_ID) {
/* Set NAND interface access parameters */
MV_REG_WRITE(NAND_READ_PARAMS_REG, BOARD_INFO(boardId)->nandFlashReadParams);
MV_REG_WRITE(NAND_WRITE_PARAMS_REG, BOARD_INFO(boardId)->nandFlashWriteParams);
MV_REG_WRITE(NAND_CTRL_REG, BOARD_INFO(boardId)->nandFlashControl);
}
/* Set GPP Out value */
MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow);
MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh);
/* set GPP polarity */
mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow);
mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh);
/* Workaround for Erratum FE-MISC-70*/
if(mvCtrlRevGet()==MV_88F6XXX_A0_REV)
{
BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd;
BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002;
} /*End of WA*/
/* Set GPP Out Enable*/
mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow);
mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh);
/* Nand CE */
MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT);
}
/*******************************************************************************
* mvGppValueSet - Set a GPP Pin list value.
*
* DESCRIPTION:
* This function set value for given GPP pin list.
*
* INPUT:
* group - GPP group number
* mask - 32bit mask value. Each set bit in the mask means that the
* value of corresponding GPP will be set accordingly. Other GPP
* are not affected.
* value - 32bit value that describes GPP value per pin.
*
* OUTPUT:
* None.
*
* EXAMPLE:
* Set GPP8 value of '0' and GPP15 value of '1'.
* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) );
*
* RETURN:
* None.
*
*******************************************************************************/
MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value)
{
MV_U32 outEnable, tmp;
MV_U32 i;
if (group >= MV_GPP_MAX_GROUP)
{
DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n"));
return MV_BAD_PARAM;
}
/* verify that the gpp pin is configured as output */
/* Note that in the register out enabled -> bit = '0'. */
outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group));
/* Workaround for Erratum FE-MISC-70*/
if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1))
{
tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0));
outEnable &= 0xfffffffd;
outEnable |= (tmp & 0x2);
} /*End of WA*/
for (i = 0 ; i < 32 ;i++)
{
if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i)))
{
mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\
"value to GPP %d in input mode.\n", i);
return MV_ERROR;
}
}
gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value);
return MV_OK;
}
/*******************************************************************************
**
** mvOnuPonMacBurstEnableInit
** ____________________________________________________________________________
**
** DESCRIPTION: The function init Burst Enable MPP
**
** PARAMETERS: None
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS mvOnuPonMacBurstEnableInit(void)
{
MV_U32 gpioGroup, gpioMask;
MV_STATUS status = MV_OK;
if (MV_6601_DEV_ID == mvCtrlModelGet())
{
/* PHY control register - output status set */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_IO_EN, ONU_PHY_OUTPUT, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl enable - output\n\r");
return(MV_ERROR);
}
/* Set SW BEN control for MC tranciever */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_SW_HW_SELECT, 1, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy SW ctrl select\n\r");
return(MV_ERROR);
}
/* PHY control register - force disable */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_SW_FORCE, 0, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy SW ctrl not force\n\r");
return(MV_ERROR);
}
} else if (mvCtrlRevGet() == ONU_ASIC_REV_Z2) {
/* KW2 ASIC Rev Z2 */
/* =============== */
PON_GPIO_GET(BOARD_GPP_PON_XVR_TX, gpioGroup, gpioMask);
if (gpioMask == PON_GPIO_NOT_USED)
return MV_ERROR;
status = mvGppTypeSet(gpioGroup, gpioMask, ~gpioMask/* 0-output allow transsmit*/);
if (status == MV_OK)
status = mvGppValueSet(gpioGroup, gpioMask, ~gpioMask/*0-disable signal*/);
else
return(status);
if (status == MV_OK)
status = mvGppTypeSet(gpioGroup, gpioMask, gpioMask /* 0-input NOT allow transsmit*/);
} else if (mvCtrlRevGet() == ONU_ASIC_REV_A0) {
/* KW2 ASIC Rev A0 */
/* =============== */
/* PHY control register - output status set */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_IO_EN, ONU_PHY_OUTPUT, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl enable - output\n\r");
return(MV_ERROR);
}
/* PHY control register - force disable */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_FORCE_BEN_IO_EN, 0, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl not force\n\r");
return(MV_ERROR);
}
}
return(status);
}
MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
MV_U32 regOff)
{
#endif
MV_U32 pexData = 0;
MV_U32 localDev,localBus;
/* Parameter checking */
if (PEX_DEFAULT_IF != pexIf)
{
if (pexIf >= mvCtrlPexMaxIfGet())
{
mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf);
return 0xFFFFFFFF;
}
}
if (dev >= MAX_PEX_DEVICES)
{
DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev));
return 0xFFFFFFFF;
}
if (func >= MAX_PEX_FUNCS)
{
DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func));
return 0xFFFFFFFF;
}
if (bus >= MAX_PEX_BUSSES)
{
DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus));
return MV_ERROR;
}
DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n",
pexIf, bus, dev, func, regOff));
localDev = mvPexLocalDevNumGet(pexIf);
localBus = mvPexLocalBusNumGet(pexIf);
/* Speed up the process. In case on no link, return MV_ERROR */
if ((dev != localDev) || (bus != localBus))
{
pexData = MV_REG_READ(PEX_STATUS_REG(pexIf));
if ((pexData & PXSR_DL_DOWN))
{
return MV_ERROR;
}
}
/* in PCI Express we have only one device number */
/* and this number is the first number we encounter
else that the localDev*/
/* spec pex define return on config read/write on any device */
if (bus == localBus)
{
if (localDev == 0)
{
/* if local dev is 0 then the first number we encounter
after 0 is 1 */
if ((dev != 1)&&(dev != localDev))
{
return MV_ERROR;
}
}
else
{
/* if local dev is not 0 then the first number we encounter
is 0 */
if ((dev != 0)&&(dev != localDev))
{
return MV_ERROR;
}
}
if(func != 0 ) /* i.e bridge */
{
return MV_ERROR;
}
}
/* Creating PEX address to be passed */
pexData = (bus << PXCAR_BUS_NUM_OFFS);
pexData |= (dev << PXCAR_DEVICE_NUM_OFFS);
pexData |= (func << PXCAR_FUNC_NUM_OFFS);
pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */
/* extended register space */
pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >>
PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
pexData |= PXCAR_CONFIG_EN;
/* Write the address to the PEX configuration address register */
MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData);
DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData));
/* In order to let the PEX controller absorbed the address of the read */
/* transaction we perform a validity check that the address was written */
if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf)))
{
return MV_ERROR;
}
/* cleaning Master Abort */
MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND),
PXSAC_MABORT);
#if 0
/* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */
/* This guideline is relevant for all devices except of the following devices:
88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above
88F6183 A0 and above, 88F6183L */
if ( ( (dev != localDev) || (bus != localBus) ) &&
(
!(MV_5281_DEV_ID == mvCtrlModelGet())&&
!((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&&
!(MV_1281_DEV_ID == mvCtrlModelGet())&&
!(MV_6183_DEV_ID == mvCtrlModelGet())&&
!(MV_6183L_DEV_ID == mvCtrlModelGet())&&
!(MV_6281_DEV_ID == mvCtrlModelGet())&&
!(MV_6192_DEV_ID == mvCtrlModelGet())&&
!(MV_6190_DEV_ID == mvCtrlModelGet())&&
!(MV_6180_DEV_ID == mvCtrlModelGet())&&
!(MV_78XX0_DEV_ID == mvCtrlModelGet())
))
{
/* PCI-Express configuration read work-around */
/* we will use one of the Punit (AHBToMbus) windows to access the xbar
and read the data from there */
/*
Need to configure the 2 free Punit (AHB to MBus bridge)
address decoding windows:
Configure the flash Window to handle Configuration space requests
for PEX0/1:
1. write 0x7931/0x7941 to the flash window and the size,
79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn
2. write base to flash window
Configuration transactions from the CPU should write/read the data
to/from address of the form:
addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1)
addr[27:24] = extended register number
addr[23:16] = bus number
addr[15:11] = device number
addr[10:8] = function number
addr[7:0] = register number
*/
#include "ctrlEnv/sys/mvAhbToMbus.h"
{
MV_U32 winNum;
MV_AHB_TO_MBUS_DEC_WIN originWin;
MV_U32 pciAddr=0;
MV_U32 remapLow=0,remapHigh=0;
/*
We will use DEV_CS2\Flash window for this workarround
*/
winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET);
/* save remap values if exist */
if ((1 == winNum)||(0 == winNum))
{
remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum));
remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum));
}
/* save the original window values */
mvAhbToMbusWinGet(winNum,&originWin);
if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES)
{
/* set the window as xbar window */
if (pexIf)
{
MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum),
(0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16));
}
else
{
MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum),
(0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16));
}
MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum),
originWin.addrWin.baseLow);
/*pciAddr = originWin.addrWin.baseLow;*/
pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(
(MV_U32)originWin.addrWin.baseLow);
}
/*******************************************************************************
* mvBoardIdGet - Get Board model
*
* DESCRIPTION:
* This function returns board ID.
* Board ID is 32bit word constructed of board model (16bit) and
* board revision (16bit) in the following way: 0xMMMMRRRR.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* 32bit board ID number, '-1' if board is undefined.
*
*******************************************************************************/
MV_U32 mvBoardIdGet(MV_VOID)
{
MV_U32 tmpBoardId = -1;
BOARD_DATA boardData;
if(gBoardId != -1)
return gBoardId;
#if defined(MV_88F1181)
if(boardEepromGet(&boardData) == MV_OK)
{
tmpBoardId = (MV_U32)boardData.boardId;
}
else
{
/* until we have relevant data in twsi then we
will detect the board type from sdram config reg */
if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
{
tmpBoardId = DB_88F1181_DDR2;
}
else
{
tmpBoardId = DB_88F1181_DDR1;
}
}
#elif defined(MV_88F5181)
if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
{
}
else /* DDR1 */
{
#if defined(RD_88F5182)
tmpBoardId = RD_88F5182_2XSATA;
#elif defined(RD_88F5182_3)
tmpBoardId = RD_88F5182_2XSATA3;
#elif defined(RD_88W8660)
tmpBoardId = RD_88W8660_DDR1;
#elif defined(RD_88F5181L_FE)
tmpBoardId = RD_88F5181L_VOIP_FE;
#elif defined(RD_88F5181L_GE)
tmpBoardId = RD_88F5181L_VOIP_GE;
#elif defined(MV_POS_NAS)
tmpBoardId = RD_88F5181_POS_NAS;
#elif defined(MV_VOIP)
tmpBoardId = RD_88F5181_VOIP;
#elif defined(DB_PRPMC)
tmpBoardId = DB_88F5181_DDR1_PRPMC;
#elif defined(DB_PEX_PCI)
tmpBoardId = DB_88F5181_DDR1_PEXPCI;
#else
tmpBoardId = RD_88F5181_POS_NAS;
#endif
}
if(tmpBoardId != -1) {
gBoardId = tmpBoardId;
return tmpBoardId;
}
//jack20060626
// if(boardEepromGet(&boardData) == MV_OK)
// {
// tmpBoardId = (MV_U32)boardData.boardId;
// }
// else
{
/* until we have relevant data in twsi then we
will detect the board type from sdram config reg */
if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2)
{
if((mvCtrlModelGet() == MV_5281_DEV_ID)&&(mvCtrlRevGet() >= 0x1))
{
tmpBoardId = DB_88F5X81_DDR2;
}
else if(mvCtrlModelGet() == MV_8660_DEV_ID)
{
tmpBoardId = DB_88W8660_DDR2;
}
else if(mvCtrlModelGet() == MV_5182_DEV_ID)
{
tmpBoardId = DB_88F5182_DDR2;
}
else
{
tmpBoardId = DB_88F5181_5281_DDR2;
}
}
else /* DDR1 */
{
if (MV_REG_READ(PCI_ARBITER_CTRL_REG(0)) & PACR_ARB_ENABLE) /* arbiter enabled*/
{
if((mvCtrlModelGet() == MV_5281_DEV_ID)&&(mvCtrlRevGet() >= 0x1))
{
tmpBoardId = DB_88F5X81_DDR1;
}
else
{
tmpBoardId = DB_88F5181_5281_DDR1;
}
}
else /* arbiter disabled */
{
if ((MV_REG_READ(PEX_CTRL_REG(0)) & PXCR_DEV_TYPE_CTRL_MASK)
== PXCR_DEV_TYPE_CTRL_CMPLX) /*root complex*/
{
tmpBoardId = DB_88F5181_DDR1_PRPMC;
}
else if ((MV_REG_READ(PEX_CTRL_REG(0)) & PXCR_DEV_TYPE_CTRL_MASK)
== PXCR_DEV_TYPE_CTRL_POINT) /*end point*/
{
tmpBoardId = DB_88F5181_DDR1_PEXPCI;
}
}
}
}
gBoardId = tmpBoardId;
return tmpBoardId;
#else
# error "CHIP not selected"
#endif
}
/*****************************************************************************
* UART
****************************************************************************/
static struct resource mv_uart_resources[] = {
{
.start = PORT0_BASE,
.end = PORT0_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_UART0,
.end = IRQ_UART0,
.flags = IORESOURCE_IRQ,
},
{
.start = PORT1_BASE,
.end = PORT1_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_UART1,
.end = IRQ_UART1,
.flags = IORESOURCE_IRQ,
},
};
static struct plat_serial8250_port mv_uart_data[] = {
{
.mapbase = PORT0_BASE,
.membase = (char *)PORT0_BASE,
.irq = IRQ_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
},
{
.mapbase = PORT1_BASE,
.membase = (char *)PORT1_BASE,
.irq = IRQ_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
},
{ },
};
static struct platform_device mv_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = mv_uart_data,
},
.num_resources = ARRAY_SIZE(mv_uart_resources),
.resource = mv_uart_resources,
};
static void serial_initialize(void)
{
mv_uart_data[0].uartclk = mv_uart_data[1].uartclk = mvTclk;
platform_device_register(&mv_uart);
}
static void __init mv_vfp_init(void)
{
#if defined CONFIG_VFP_FASTVFP
printk("VFP initialized to Run Fast Mode.\n");
#endif
}
#if defined(MV_88F6183)
#ifdef CONFIG_MV_INCLUDE_AUDIO
typedef struct {
unsigned int base;
unsigned int size;
} _audio_mem_info;
typedef struct {
u32 spdif_rec;
u32 spdif_play;
u32 i2s_rec;
u32 i2s_play;
_audio_mem_info mem_array[MV_DRAM_MAX_CS + 1];
} _audio_info;
_audio_info audio_info = {1, 1, 1, 1};
static struct resource mv_snd_resources[] = {
[0] = {
.start = INTER_REGS_BASE + AUDIO_REG_BASE,
.end = INTER_REGS_BASE + AUDIO_REG_BASE + SZ_16K -1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_AUDIO_INT,
.end = IRQ_AUDIO_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = NR_IRQS, /* should obtained from board information*/
.end = NR_IRQS, /* should obtained from board information */
.flags = IORESOURCE_IRQ,
}
};
static u64 mv_snd_dmamask = 0xFFFFFFFFUL;
static struct platform_device mv_snd_device = {
.name = "mv88fx_snd",
.id = -1,
.dev = {
.dma_mask = &mv_snd_dmamask,
.coherent_dma_mask = 0xFFFFFFFF,
.platform_data = &audio_info,
},
.num_resources = ARRAY_SIZE(mv_snd_resources),
.resource = mv_snd_resources,
};
#endif /* #ifdef CONFIG_MV_INCLUDE_AUDIO */
#ifdef CONFIG_MV_INCLUDE_SDIO
static struct resource mvsdmmc_resources[] = {
[0] = {
.start = INTER_REGS_BASE + 0x80000,
.end = INTER_REGS_BASE + 0x80000 + SZ_1K -1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = SDIO_IRQ_NUM,
.end = SDIO_IRQ_NUM,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = NR_IRQS, /* should obtained from board information*/
.end = NR_IRQS, /* should obtained from board information */
.flags = IORESOURCE_IRQ,
}
};
static u64 mvsdmmc_dmamask = 0xffffffffUL;
static struct platform_device mvsdmmc_device = {
.name = "mvsdmmc",
.id = -1,
.dev = {
.dma_mask = &mvsdmmc_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(mvsdmmc_resources),
.resource = mvsdmmc_resources,
};
#endif /* CONFIG_MV_INCLUDE_SDIO */
static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_MV_INCLUDE_AUDIO
&mv_snd_device,
#endif
#ifdef CONFIG_MV_INCLUDE_SDIO
&mvsdmmc_device,
#endif
NULL
};
#endif /* #if defined(MV_88F6183) */
static void __init mv_init(void)
{
unsigned int temp;
/* init the Board environment */
if (mvBoardIdGet() != RD_88F6082_MICRO_DAS_NAS) /* excluded for HDD power problem - to be fixed */
mvBoardEnvInit();
/* init the controller environment */
if( mvCtrlEnvInit() ) {
printk( "Controller env initialization failed.\n" );
return;
}
if(mvBoardIdGet() == RD_88F5181_POS_NAS) {
temp = MV_REG_READ(GPP_DATA_OUT_REG(0));
temp &= ~(1 << 0x5);
/* for host mode should be set to 0 */
if(!mvIsUsbHost) {
temp |= (1 << 0x5);
}
MV_REG_WRITE(GPP_DATA_OUT_REG(0), temp);
}
/* Init the CPU windows setting and the access protection windows. */
if( mvCpuIfInit(mv_sys_map()) ) {
printk( "Cpu Interface initialization failed.\n" );
return;
}
/* Init Tclk & SysClk */
mvTclk = mvBoardTclkGet();
mvSysclk = mvBoardSysClkGet();
printk("Sys Clk = %d, Tclk = %d\n",mvSysclk ,mvTclk );
if ((mvCtrlModelGet() == MV_5281_DEV_ID) || (mvCtrlModelGet() == MV_1281_DEV_ID)
|| (mvCtrlModelGet() == MV_6183_DEV_ID))
mv_orion_ver = MV_ORION2; /* Orion II */
else
mv_orion_ver = MV_ORION1; /* Orion I */
/* Implement workaround for FEr# CPU-C16: Wait for interrupt command */
/* is not processed properly, the workaround is not to use this command */
/* the erratum is relevant for 5281 devices with revision less than C0 */
if((mvCtrlModelGet() == MV_5281_DEV_ID)
&& (mvCtrlRevGet() < MV_5281_C0_REV))
{
support_wait_for_interrupt = 0;
}
#ifdef CONFIG_JTAG_DEBUG
support_wait_for_interrupt = 0; /* for Lauterbach */
#endif
mv_vfp_init();
elf_hwcap &= ~HWCAP_JAVA;
serial_initialize();
/* At this point, the CPU windows are configured according to default definitions in mvSysHwConfig.h */
/* and cpuAddrWinMap table in mvCpuIf.c. Now it's time to change defaults for each platform. */
mvCpuIfAddDecShow();
#if defined(CONFIG_MTD_PHYSMAP)
mv_mtd_initialize();
#endif
print_board_info();
#ifdef CONFIG_MV_INCLUDE_IDMA
mvDmaInit();
#endif
#if defined(MV_88F6183)
#ifdef CONFIG_MV_INCLUDE_SDIO
mvsdmmc_resources[2].end = mvBoardSDIOGpioPinGet() + IRQ_GPP_START;
mvsdmmc_resources[2].start = mvBoardSDIOGpioPinGet() + IRQ_GPP_START;
irq_int_type[mvBoardSDIOGpioPinGet()] = GPP_IRQ_TYPE_CHANGE_LEVEL;
#endif /* CONFIG_MV_INCLUDE_SDIO */
#ifdef CONFIG_MV_INCLUDE_AUDIO
for (temp=0 ; temp< MV_DRAM_MAX_CS; temp++) {
MV_DRAM_DEC_WIN win;
audio_info.mem_array[temp].base = 0;
audio_info.mem_array[temp].size = 0;
mvDramIfWinGet(SDRAM_CS0 + temp, &win);
if (win.enable) {
audio_info.mem_array[temp].base = win.addrWin.baseLow;
audio_info.mem_array[temp].size = win.addrWin.size;
}
}
#endif /* CONFIG_MV_INCLUDE_AUDIO */
if ((temp = ARRAY_SIZE(devices) - 1))
platform_add_devices(devices, temp);
#endif /* MV_88F6183 */
return;
}
/*******************************************************************************
* mvSysUsbHalInit - Initialize the USB subsystem
*
* DESCRIPTION:
*
* INPUT:
* None
* OUTPUT:
* None
* RETURN:
* None
*
*******************************************************************************/
MV_STATUS mvSysUsbInit(MV_VOID)
{
MV_USB_HAL_DATA halData;
MV_STATUS status = MV_OK;
MV_U32 dev;
MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1];
halData.ctrlModel = mvCtrlModelGet();
halData.ctrlRev = mvCtrlRevGet();
halData.ctrlFamily = mvCtrlDevFamilyIdGet(halData.ctrlModel);
status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1);
#ifdef CONFIG_USB_EHCI
MV_BOOL isHost;
char envname[10], *env;
int maxUsbPorts = mvCtrlUsbMaxGet();
/* for ALP/A375: if using single usb2 port, use Virtual MAC ID since
MAC ID0 (usbActive =0) is connected to Physical MAC ID1 */
int id, mac_id[2] = {1, 0};
for (id = 0; id < maxUsbPorts ; id++) {
if (mvBoardIsUsbPortConnected(USB_UNIT_ID,id) == MV_FALSE)
continue;
if (maxUsbPorts == 1 && (halData.ctrlFamily == MV_88F67X0 ||
(halData.ctrlRev == MV_88F66XX_A0_ID && halData.ctrlFamily == MV_88F66X0)))
dev = mac_id[id];
else
dev = id;
sprintf(envname, "usb%dMode", dev);
env = getenv(envname);
if ((!env) || (strcmp(env, "device") == 0) || (strcmp(env, "Device") == 0))
isHost = MV_FALSE;
else
isHost = MV_TRUE;
if (status == MV_OK) /* Map DDR windows to EHCI */
#ifdef CONFIG_USB_XHCI_HCD
/* CONFIG_USB_XHCI_HCD indicate that both xHCI and eHCI are compiled:
* Last Boolean argument is used to indicate the HAL layer which unit is currently initiated */
status = mvUsbWinInit(dev, addrWinMap, MV_FALSE);
#else
status = mvUsbWinInit(dev, addrWinMap);
#endif
if (status == MV_OK)
status = mvUsbHalInit(dev, isHost, &halData);
if (status == MV_OK)
printf("USB2.0 %d: %s Mode\n", dev, (isHost == MV_TRUE ? "Host" : "Device"));
else
mvOsPrintf("%s: Error: USB2.0 initialization failed (port %d).\n", __func__, dev);
}
#endif
#ifdef CONFIG_USB_XHCI
MV_U32 reg;
for (dev = 0; dev < mvCtrlUsb3HostMaxGet(); dev++) {
if (mvBoardIsUsbPortConnected(USB3_UNIT_ID,dev) == MV_FALSE)
continue;
status = mvUsbUtmiPhyInit(dev, &halData);
if (halData.ctrlFamily == MV_88F66X0 || halData.ctrlFamily == MV_88F67X0) {
/* ALP/A375: Set UTMI PHY Selector:
* - Connect UTMI PHY to USB2 port of USB3 Host
* - Powers down the other unit (so USB3.0 unit's registers are accessible) */
reg = MV_REG_READ(USB_CLUSTER_CONTROL);
reg = (reg & (~0x1)) | 0x1;
MV_REG_WRITE(USB_CLUSTER_CONTROL, reg);
}
if (status == MV_OK) /* Map DDR windows to XHCI */
status = mvUsbWinInit(mvCtrlUsbMapGet(USB3_UNIT_ID, dev), addrWinMap, MV_TRUE);
if (status == MV_OK)
printf("USB3.0 %d: Host Mode\n", mvCtrlUsbMapGet(USB3_UNIT_ID, dev));
else
mvOsPrintf("%s: Error: USB3.0 initialization failed (port %d).\n", __func__,
mvCtrlUsbMapGet(USB3_UNIT_ID, dev));
}
#endif
return status;
}
/*******************************************************************************
**
** onuPonPatternBurstOn
** ____________________________________________________________________________
**
** DESCRIPTION: The function start TX transmissions of a selected pattern as periodic or static burst
**
** PARAMETERS:
** MV_U32 pattern 0x1 1T
** 0x2 2T
** 0x80 PRBS - 9
** 0x82 PRBS - 15
** 0x83 PRBS - 23
** MV_BOOL isPeriodic TX burst can be either static (in this case the following parameters has no effect)
** and this parameter is FALSE OR periodic in this case this parameters is TRUE
** MV_U32 period cycle time - the time in micro seconds between the start of on peak and the other
** (must be greater then the duration interval)
** MV_U32 duration peak time interval in micro seconds (must be smaller then the duration interval)
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuPonPatternBurstOn(MV_U32 pattern, MV_BOOL isPeriodic, MV_U32 period, MV_U32 duration)
{
MV_STATUS status;
/*pattern validation*/
if (!((pattern == ONU_PON_TX_PATTERN_TYPE_T1) ||
(pattern == ONU_PON_TX_PATTERN_TYPE_T2) ||
(pattern == ONU_PON_TX_PATTERN_TYPE_PRBS_9) ||
(pattern == ONU_PON_TX_PATTERN_TYPE_PRBS_15) ||
(pattern == ONU_PON_TX_PATTERN_TYPE_PRBS_23))) {
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE, "Wrong pattern type value %d \n", pattern);
return MV_BAD_VALUE;
}
if ((isPeriodic == MV_TRUE) && (duration >= period)) {
mvPonPrint(PON_PRINT_ERROR, PON_INIT_MODULE,
"Period value %d MUST be greater then duration value %d \n", period, duration);
return MV_BAD_VALUE;
}
/*in case of sequential call to onuPonPatternBurstOn*/
/*stop timer operation and transmissions*/
onuPonTimerDisable(&(onuPonResourceTbl_s.onuPonPatternBurstTimerId));
onuPonPatternBurstTransmit(MV_TRUE);
onuPonPatternBurstEnable(MV_FALSE);
time_interval_up = 0;
time_interval_down = 0;
if (mvCtrlRevGet() == ONU_ASIC_REV_Z2) {
/* ASIC Rev Z2 */
/* =========== */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_IO_EN, ONU_PHY_INPUT, 0);
if (status != MV_OK)
return(status);
} else if (mvCtrlRevGet() == ONU_ASIC_REV_A0) {
/* ASIC Rev A0 */
/* =========== */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_IO_EN, ONU_PHY_OUTPUT, 0);
if (status != MV_OK)
return(status);
}
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_INTERNAL_EN_LOOP_TIMING, 0x0, 0);
if (status != MV_OK)
return(status);
/*Set system in PHY mode, meaning disconnect the PON MAC*/
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_INTERNAL_OPEN_TX_DOOR_15, 0x1, 0);
if (status != MV_OK)
return(status);
/*Set sedes power up in phy mode*/
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_POWER_PHY_MODE, 0xfd04,0);
if (status != MV_OK)
return(status);
/*set select on pattern*/
status = asicOntMiscRegWrite(mvAsicReg_PT_PATTERN_SELECT, 0x7, 0);
if (status != MV_OK)
return(status);
/*set pattern type*/
status = asicOntMiscRegWrite(mvAsicReg_PT_PATTERN_DATA, pattern, 0);
if (status != MV_OK)
return(status);
/*turn on selected pattern*/
status = asicOntMiscRegWrite(mvAsicReg_PT_PATTERN_ENABLED, 0x1, 0);
if (status != MV_OK)
return(status);
onuPonPatternBurstEnable(MV_TRUE);
if (isPeriodic == MV_TRUE) {
/*periosic burst*/
time_interval_up = duration;
time_interval_down = (period - duration);
transmit_up = MV_TRUE;
onuPonTimerUpdate(&(onuPonResourceTbl_s.onuPonPatternBurstTimerId),0,time_interval_up,1);
}
return(MV_OK);
}
/*******************************************************************************
**
** onuPonPatternBurstEnable
** ____________________________________________________________________________
**
** DESCRIPTION:
**
** PARAMETERS: bool on
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuPonPatternBurstEnable(bool on)
{
MV_STATUS status;
MV_U32 gpioGroup, gpioMask;
MV_U32 trans_value = 0;
MV_U32 polarity;
if (MV_6601_DEV_ID == mvCtrlModelGet())
{
/* PHY control register - force enable */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_SW_FORCE, 1, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy SW ctrl force\n\r");
return(MV_ERROR);
}
/* PHY control register - force enable value - according to polarity */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_SW_VALUE, 1, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl SW force value %d\n\r",
trans_value);
return(MV_ERROR);
}
} else if (mvCtrlRevGet() == ONU_ASIC_REV_Z2) {
/* ASIC Rev Z2 */
/* =========== */
PON_GPIO_GET(BOARD_GPP_PON_XVR_TX, gpioGroup, gpioMask);
if (gpioMask == PON_GPIO_NOT_USED)
return MV_ERROR;
trans_value = ((on == MV_TRUE) ? (gpioMask/*1*/) : (~gpioMask/*0*/));
status = mvGppValueSet(gpioGroup, gpioMask, trans_value);
if (status != MV_OK)
return(MV_ERROR);
} else if (mvCtrlRevGet() == ONU_ASIC_REV_A0) {
/* ASIC Rev A0 */
/* =========== */
/* PHY control register - force enable */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_FORCE_BEN_IO_EN, 1, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl force\n\r");
return(MV_ERROR);
}
polarity = onuP2PDbXvrBurstEnablePolarityGet();
/* XVR polarity */
/* XVR polarity == 0, Active High, transmit 1 to the line */
/* XVR polarity == 1, Active Low, transmit 0 to the line */
/* P2P mode */
/* Force Value == 0, transmit 0 to the line */
/* Force Value == 1, transmit 1 to the line */
/* Setting P2P should be reversed from XVR polarity */
/* XVR polarity == 0, Active High, write 1 for Force Value */
/* XVR polarity == 1, Active Low, write 0 for Force Value */
/* PHY control register - force enable value - according to polarity */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_FORCE_BEN_IO_VAL, polarity, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl force value %d\n\r",
trans_value);
return(MV_ERROR);
}
}
transmit_up = on;
return(MV_OK);
}
/* USB Phy init (change from defaults) for 150nm chips:
* - 645xx, 646xx
* - 51xx, 52xx
* - 6082
*/
static void mvUsbPhyInit(int dev)
{
MV_U32 regVal;
/* GL# USB-9 */
/******* USB 2.0 Power Control Register 0x400 *******/
regVal= MV_REG_READ(MV_USB_PHY_POWER_CTRL_REG(dev));
/* Bits 7:6 (BG_VSEL) = 0x1 */
regVal &= ~(0x3 << 6);
regVal |= (0x1 << 6);
MV_REG_WRITE(MV_USB_PHY_POWER_CTRL_REG(dev),regVal);
/* GL# USB-1 */
/******* USB PHY Tx Control Register Register 0x420 *******/
regVal = MV_REG_READ(MV_USB_PHY_TX_CTRL_REG(dev));
if( (mvCtrlModelGet() == MV_5181_DEV_ID) && (mvCtrlRevGet() <= MV_5181_A1_REV) )
{
/* For OrionI A1/A0 rev: Bit[21] = 0 (TXDATA_BLOCK_EN = 0). */
regVal &= ~(1 << 21);
}
else
{
regVal |= (1 << 21);
}
/* Force Auto calibration */
/* Bit[13] = 0x1, (REG_EXT_RCAL_EN = 0x1) */
regVal |= (1<<13);
/* Bits[2:0] (TxAmp)
* 64560, 64660, 6082, 5181, 5182, etc = 0x4
* 5281 = 0x3
*/
if(mvCtrlModelGet() == MV_5281_DEV_ID)
{
regVal &= ~(0x7 << 0);
regVal |= (0x3 << 0);
}
else
{
regVal &= ~(0x7 << 0);
regVal |= (0x4 << 0);
}
/* Bit[6:3] (IMP_CAL)
* 64560, 64660 = 0xA
* Others = 0x8
*
*/
regVal &= ~(0xf << 3);
if( (mvCtrlModelGet() == MV64560_DEV_ID) ||
(mvCtrlModelGet() == MV64660_DEV_ID))
{
regVal |= (0xA << 3);
}
else
{
regVal |= (0x8 << 3);
}
MV_REG_WRITE(MV_USB_PHY_TX_CTRL_REG(dev), regVal);
/* GL# USB-3 GL# USB-9 */
/******* USB PHY Rx Control Register 0x430 *******/
regVal = MV_REG_READ(MV_USB_PHY_RX_CTRL_REG(dev));
/* bit[8:9] - (DISCON_THRESHOLD ). */
/* 88F5181-A0/A1/B0 = 11, 88F5281-A0 = 10, all other 00 */
/* 64660-A0 = 10 */
regVal &= ~(0x3 << 8);
if( (mvCtrlModelGet() == MV_5181_DEV_ID) && (mvCtrlRevGet() <= MV_5181_B0_REV) )
{
regVal |= (0x3 << 8);
}
else if(mvCtrlModelGet() == MV64660_DEV_ID)
{
regVal |= (0x2 << 8);
}
/* bit[21] = 0 (CDR_FASTLOCK_EN = 0). */
regVal &= ~(1 << 21);
/* bit[27:26] = 00 ( EDGE_DET_SEL = 00). */
regVal &= ~(0x3 << 26);
/* Bits[31:30] = RXDATA_BLOCK_LENGHT = 0x3 */
regVal |= (0x3 << 30);
/* Bits 7:4 (SQ_THRESH)
* 64560, 64660 = 0x1
* 5181, 5182, 5281, 6082, etc = 0x0
*/
regVal &= ~(0xf << 4);
if( (mvCtrlModelGet() == MV64560_DEV_ID) ||
(mvCtrlModelGet() == MV64660_DEV_ID))
{
regVal |= (0x1 << 4);
}
MV_REG_WRITE(MV_USB_PHY_RX_CTRL_REG(dev), regVal);
/* GL# USB-3 GL# USB-9 */
/******* USB PHY IVREF Control Register 0x440 *******/
regVal = MV_REG_READ(MV_USB_PHY_IVREF_CTRL_REG(dev));
/*Bits[1:0] = 0x2 (PLLVDD12 = 0x2)*/
regVal &= ~(0x3 << 0);
regVal |= (0x2 << 0);
/* Bits 5:4 (RXVDD) = 0x3; */
regVal &= ~(0x3 << 4);
regVal |= (0x3 << 4);
/* <VPLLCAL> bits[17:16] = 0x1 */
if( (mvCtrlModelGet() == MV64560_DEV_ID) ||
(mvCtrlModelGet() == MV64660_DEV_ID))
{
regVal &= ~(0x3 << 16);
regVal |= (0x1 << 16);
}
/* <ISAMPLE_SEL> bits[19:18] = 0x2 */
regVal &= ~(0x3 << 18);
regVal |= (0x2 << 18);
/* <SAMPLER_CTRL> bit[20] = 0x0 */
regVal &= ~(0x1 << 20);
/* <ICHGPBUF_SEL> bit[21] = 0x1 */
regVal |= (0x1 << 21);
MV_REG_WRITE(MV_USB_PHY_IVREF_CTRL_REG(dev), regVal);
/***** USB PHY TEST GROUP CONTROL Register: 0x450 *****/
regVal = MV_REG_READ(MV_USB_PHY_TEST_GROUP_CTRL_REG_0(dev));
/* bit[15] = 0 (REG_FIFO_SQ_RST = 0). */
regVal &= ~(1 << 15);
/* <REG_FIFO_OVUF_SEL> bit[17] = 0x1 */
if( (mvCtrlModelGet() == MV64560_DEV_ID) ||
(mvCtrlModelGet() == MV64660_DEV_ID))
{
regVal |= (1 << 17);
}
MV_REG_WRITE(MV_USB_PHY_TEST_GROUP_CTRL_REG_0(dev), regVal);
}
/*******************************************************************************
* mvUsbHalInit - Initialize USB engine
*
* DESCRIPTION:
* This function initialize USB unit. It set the default address decode
* windows of the unit.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if setting fail.
*******************************************************************************/
MV_STATUS mvUsbHalInit(int dev, MV_BOOL isHost)
{
MV_U32 regVal;
/* Clear Interrupt Cause and Mask registers */
MV_REG_WRITE(MV_USB_BRIDGE_INTR_CAUSE_REG(dev), 0);
MV_REG_WRITE(MV_USB_BRIDGE_INTR_MASK_REG(dev), 0);
/* Reset controller */
regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev));
MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal | MV_USB_CORE_CMD_RESET_MASK);
while( MV_REG_READ(MV_USB_CORE_CMD_REG(dev)) & MV_USB_CORE_CMD_RESET_MASK);
/* Clear bit 4 in USB bridge control register for enableing core byte swap */
if((mvCtrlModelGet() == MV64560_DEV_ID) || (mvCtrlModelGet() == MV64660_DEV_ID))
{
MV_REG_WRITE(MV_USB_BRIDGE_CTRL_REG(dev),(MV_REG_READ(MV_USB_BRIDGE_CTRL_REG(dev))
& ~MV_USB_BRIDGE_CORE_BYTE_SWAP_MASK));
}
/* GL# USB-10 */
/* The new register 0x360 USB 2.0 IPG Metal Fix Register
* dont' exists in the following chip revisions:
* OrionN B1 (id=0x5180, rev 3)
* Orion1 B1 (id=0x5181, rev=3) and before
* Orion1-VoIP A0 (id=0x5181, rev=8)
* Orion1-NAS A1 (id=0x5182, rev=1) and before
* Orion2 B0 (id=0x5281, rev=1) and before
*/
if( ((mvCtrlModelGet() == MV_5181_DEV_ID) &&
((mvCtrlRevGet() <= MV_5181_B1_REV) || (mvCtrlRevGet() == MV_5181L_A0_REV))) ||
((mvCtrlModelGet() == MV_5182_DEV_ID) &&
(mvCtrlRevGet() <= MV_5182_A1_REV)) ||
((mvCtrlModelGet() == MV_5180_DEV_ID) &&
(mvCtrlRevGet() <= MV_5180N_B1_REV)) )
{
/* Do nothing */
}
else
{
/* Change value of new register 0x360 */
regVal = MV_REG_READ(MV_USB_BRIDGE_IPG_REG(dev));
/* Change bits[14:8] - IPG for non Start of Frame Packets
* from 0x9(default) to 0xD
*/
regVal &= ~(0x7F << 8);
regVal |= (0xD << 8);
MV_REG_WRITE(MV_USB_BRIDGE_IPG_REG(dev), regVal);
}
/********* Update USB PHY configuration **********/
if( (mvCtrlModelGet() == MV_78100_DEV_ID) ||
(mvCtrlModelGet() == MV_78200_DEV_ID) ||
(mvCtrlModelGet() == MV_76100_DEV_ID) ||
(mvCtrlModelGet() == MV_6281_DEV_ID) ||
(mvCtrlModelGet() == MV_6192_DEV_ID) ||
(mvCtrlModelGet() == MV_6190_DEV_ID) ||
(mvCtrlModelGet() == MV_6180_DEV_ID))
{
mvUsbPhy65nmNewInit(dev);
}
else if((mvCtrlModelGet() == MV_78XX0_DEV_ID))
{
mvUsbPhy65nmInit(dev);
}
else if( mvCtrlModelGet() == MV_6183_DEV_ID )
{
mvUsbPhy90nmInit(dev);
}
else
{
mvUsbPhyInit(dev);
}
/* Set Mode register (Stop and Reset USB Core before) */
/* Stop the controller */
regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev));
regVal &= ~MV_USB_CORE_CMD_RUN_MASK;
MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal);
/* Reset the controller to get default values */
regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev));
regVal |= MV_USB_CORE_CMD_RESET_MASK;
MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal);
/* Wait for the controller reset to complete */
do
{
regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev));
} while (regVal & MV_USB_CORE_CMD_RESET_MASK);
/* Set USB_MODE register */
if(isHost)
{
regVal = MV_USB_CORE_MODE_HOST;
}
else
{
regVal = MV_USB_CORE_MODE_DEVICE | MV_USB_CORE_SETUP_LOCK_DISABLE_MASK;
}
#if (MV_USB_VERSION == 0)
regVal |= MV_USB_CORE_STREAM_DISABLE_MASK;
#endif
MV_REG_WRITE(MV_USB_CORE_MODE_REG(dev), regVal);
return MV_OK;
}
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor;
unsigned int i;
MV_GPP_HAL_DATA gppHalData;
clock_divisor = (CONFIG_SYS_TCLK / 16)/115200;
/* muti-core support, initiate each Uart to each cpu */
mvUartInit(whoAmI(), clock_divisor, mvUartBase(whoAmI()));
if (whoAmI() != 0)
return 0;
#if defined(MV_INCLUDE_TWSI)
MV_TWSI_ADDR slave;
#endif
maskAllInt();
/* must initialize the int in order for udelay to work */
/* interrupt_init(); - no interrupt handling in u-boot */
timer_init();
/* Init the Board environment module (device bank params init) */
mvBoardEnvInit();
#if defined(MV_INCLUDE_TWSI)
slave.type = ADDR7_BIT;
slave.address = 0;
mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0);
#endif
/* Init the Controlloer environment module (MPP init) */
mvCtrlEnvInit();
#if defined(CONFIG_DISPLAY_CPUINFO)
late_print_cpuinfo(); /* display cpu info (and speed) */
#endif
mvBoardDebugLed(2);
/* Init the Controller CPU interface */
mvCpuIfInit(mvCpuAddrWinMap);
#if defined(MV_NOR_BOOT)
env_init();
#endif
if (mvBoardCpssBoardIdSet(mvBoardIdGet()) != MV_OK)
printf("%s: Error: Failed to set Board ID for CPSS!\n", __func__);
/* Init the GPIO sub-system */
gppHalData.ctrlRev = mvCtrlRevGet();
mvGppInit(&gppHalData);
/* arch number of Integrator Board */
gd->bd->bi_arch_number=mv_get_arch_number();
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
/* relocate the exception vectors */
/* U-Boot is running from DRAM at this stage */
for(i = 0; i < 0x100; i+=4) {
*(unsigned int *)(0x0 + i) = *(unsigned int*)(CONFIG_SYS_TEXT_BASE + i);
}
mvBoardDebugLed(4);
return 0;
}
