/*******************************************************************************
**
** onuPonLedInit
** ____________________________________________________________________________
**
** DESCRIPTION: The function init led operation
**
** PARAMETERS: None
**
** OUTPUTS: None
**
** RETURNS: MV_OK or MV_ERROR
**
*******************************************************************************/
MV_STATUS onuPonLedInit(void)
{
MV_STATUS status;
MV_U32 gpioGroup, gpioMask;
PON_GPIO_GET(BOARD_GPP_SYS_LED, gpioGroup, gpioMask);
if (gpioMask != PON_GPIO_NOT_USED) {
status = mvGppTypeSet(gpioGroup, gpioMask, 0/*output*/);
if (status != MV_OK)
return(status);
}
PON_GPIO_GET(BOARD_GPP_PON_LED, gpioGroup, gpioMask);
if (gpioMask != PON_GPIO_NOT_USED) {
status = mvGppTypeSet(gpioGroup, gpioMask, 0/*output*/);
if (status != MV_OK)
return(status);
}
status = asicOntMiscRegWrite(mvAsicReg_PON_LED_BLINK_FREQ_A_ON, 0x30000000, 0);
if (status != MV_OK)
return(status);
status = asicOntMiscRegWrite(mvAsicReg_PON_LED_BLINK_FREQ_A_OFF, 0x30000000, 0);
if (status != MV_OK)
return(status);
status = asicOntMiscRegWrite(mvAsicReg_PON_LED_BLINK_FREQ_B_ON, 0x15000000, 0);
if (status != MV_OK)
return(status);
status = asicOntMiscRegWrite(mvAsicReg_PON_LED_BLINK_FREQ_B_OFF, 0x15000000, 0);
return(status);
}
/* GPIO Settings for Back voltage problem workaround */
MV_U8 mvUsbGppInit(int dev)
{
MV_U32 regVal;
MV_U8 gppNo = (MV_U8)mvBoardUSBVbusGpioPinGet(dev);
MV_U8 gppVbusEnNo = (MV_U8)mvBoardUSBVbusEnGpioPinGet(dev);
/* DDR1 => gpp5, DDR2 => gpp1 */
if(gppNo != (MV_U8)N_A)
{
/*mvOsPrintf("mvUsbGppInit: gppNo=%d\n", gppNo);*/
/* MPP Control Register - set to GPP*/
regVal = MV_REG_READ(mvCtrlMppRegGet((unsigned int)(gppNo/8)));
regVal &= ~(0xf << ((gppNo%8)*4));
MV_REG_WRITE(mvCtrlMppRegGet((unsigned int)(gppNo/8)), regVal);
if(gppNo < 32)
{
/* GPIO Data Out Enable Control Register - set to input*/
mvGppTypeSet(0, (1<<gppNo), MV_GPP_IN & (1<<gppNo) );
/* GPIO Data In Polarity Register */
mvGppPolaritySet(0, (1<<gppNo), (0<<gppNo) );
}
else
{
/* GPIO Data Out Enable Control Register - set to input*/
mvGppTypeSet(1, (1<<(gppNo-32)), MV_GPP_IN & (1<<(gppNo-32)) );
/* GPIO Data In Polarity Register */
mvGppPolaritySet(1, (1<<(gppNo-32)), (0<<(gppNo-32)) );
}
/* GPIO Data In Polarity Register */
/* mvGppPolaritySet(mppGrp, (1<<gppNo), (0<<gppNo) ); */
regVal = MV_REG_READ(MV_USB_PHY_POWER_CTRL_REG(dev));
regVal &= ~(7 << 24);
MV_REG_WRITE(MV_USB_PHY_POWER_CTRL_REG(dev), regVal);
}
/* for device - reset vbus enable gpp, for host - set by default */
if(gppVbusEnNo != (MV_U8)N_A)
{
/*mvOsPrintf("mvUsbGppInit: gppVbusEnNo = %d \n", gppVbusEnNo);*/
regVal = MV_REG_READ(GPP_DATA_OUT_REG((gppVbusEnNo/32)));
if(gppVbusEnNo < 32)
{
MV_REG_WRITE(GPP_DATA_OUT_REG(0), (regVal & ~(1 << gppVbusEnNo)));
}
else
{
MV_REG_WRITE(GPP_DATA_OUT_REG(1), (regVal & ~(1 << (gppVbusEnNo - 32))));
}
}
return gppNo;
}
MV_VOID bfGppOutEnableRegBitClr(MV_32 bit)
{
if (bit < 0)
return;
if (bit < 32)
mvGppTypeSet(0, BIT(bit), 0x0);
else
mvGppTypeSet(1, BIT(bit - 32), 0x0);
}
/*******************************************************************************
**
** onuPonTxPowerControlInit
** ____________________________________________________________________________
**
** DESCRIPTION: The function initialyzes TX power control pins
**
** PARAMETERS: None
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuPonTxPowerControlInit(void)
{
MV_U32 gpioPinNum, gpioGroup, gpioMask;
MV_U32 regVal, mppGroup;
MV_GPP_HAL_DATA halData;
MV_U32 devId = mvCtrlModelGet();
MV_STATUS status = MV_OK;
gpioPinNum = mvBoarGpioPinNumGet(BOARD_GPP_PON_XVR_TX_POWER, 0);
if (gpioPinNum != MV_ERROR) {
mppGroup = mvCtrlMppRegGet(gpioPinNum / 8);
/* Set TX power MPP to GPP mode */
regVal = MV_REG_READ(mppGroup);
regVal &= ~(0xf << ((gpioPinNum % 8) * 4));
MV_REG_WRITE(mppGroup, regVal);
halData.ctrlRev = mvCtrlRevGet();
status = mvGppInit(&halData);
if (status == MV_OK) {
/* Set TX power GPP pin direction to OUT */
gpioGroup = gpioPinNum / 32;
gpioMask = 1 << gpioPinNum;
status = mvGppTypeSet(gpioGroup, gpioMask, (MV_GPP_OUT & gpioMask));
}
} else if (devId == MV_6601_DEV_ID)
status = MV_ERROR;
return(status);
}
/*******************************************************************************
**
** onuPonPatternBurstTransmit
** ____________________________________________________________________________
**
** DESCRIPTION: The function turn on or off actuacl burst transmission
**
** PARAMETERS: when on == true transmission is on
** when off == false transmission is off
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuPonPatternBurstTransmit(MV_BOOL on)
{
MV_STATUS status;
MV_U32 gpioGroup, gpioMask;
MV_U32 trans_value = 0;
if (mvCtrlRevGet() == ONU_ASIC_REV_Z2) {
/* ASIC Rev Z2 */
/* =========== */
PON_GPIO_GET(BOARD_GPP_PON_XVR_TX, gpioGroup, gpioMask);
if (gpioMask == PON_GPIO_NOT_USED)
return(MV_ERROR);
trans_value = (on == MV_TRUE ? ~gpioMask /*0*/: gpioMask /*1*/);
status = mvGppTypeSet(gpioGroup, gpioMask, trans_value);
if (status != MV_OK)
return(MV_ERROR);
} else if (mvCtrlRevGet() == ONU_ASIC_REV_A0) {
/* ASIC Rev A0 */
/* =========== */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_IO_EN, ONU_PHY_OUTPUT, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl enable - output\n\r");
return(MV_ERROR);
}
}
transmit_up = on;
return(MV_OK);
}
MV_VOID mvBoardEnvInit(MV_VOID)
{
MV_U32 boardId= mvBoardIdGet();
if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
{
mvOsPrintf("mvBoardEnvInit:Board unknown.\n");
return;
}
if (mvBoardIdGet() != XCAT98DX_ID) {
/* Set NAND interface access parameters */
MV_REG_WRITE(NAND_READ_PARAMS_REG, BOARD_INFO(boardId)->nandFlashReadParams);
MV_REG_WRITE(NAND_WRITE_PARAMS_REG, BOARD_INFO(boardId)->nandFlashWriteParams);
MV_REG_WRITE(NAND_CTRL_REG, BOARD_INFO(boardId)->nandFlashControl);
}
/* Set GPP Out value */
MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow);
MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh);
/* set GPP polarity */
mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow);
mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh);
/* Workaround for Erratum FE-MISC-70*/
if(mvCtrlRevGet()==MV_88F6XXX_A0_REV)
{
BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd;
BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002;
} /*End of WA*/
/* Set GPP Out Enable*/
mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow);
mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh);
/* Nand CE */
MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT);
}
static MV_VOID gflt200BoardInit(MV_BOARD_INFO *pBoardInfo)
{
MV_U32 board_ver;
mvGppTypeSet(0, GFLT200_GPP_BOARD_VER_MASK, GFLT200_GPP_BOARD_VER_MASK);
switch ((board_ver = mvGppValueGet(0, GFLT200_GPP_BOARD_VER_MASK))) {
case GFLT200_EVT1_BOARD_VER:
pBoardInfo->numBoardMppConfigValue
= MV_ARRAY_SIZE(gflt200Evt1InfoBoardMppConfigValue);
pBoardInfo->pBoardMppConfigValue
= gflt200Evt1InfoBoardMppConfigValue;
pBoardInfo->numBoardGppInfo
= MV_ARRAY_SIZE(gflt200Evt1InfoBoardGppInfo),
pBoardInfo->pBoardGppInfo = gflt200Evt1InfoBoardGppInfo,
pBoardInfo->gppOutEnValLow = GFLT200_EVT1_GPP_OUT_ENA_LOW;
pBoardInfo->gppOutEnValMid = GFLT200_EVT1_GPP_OUT_ENA_MID;
pBoardInfo->gppOutValLow = GFLT200_EVT1_GPP_OUT_VAL_LOW;
pBoardInfo->gppOutValMid = GFLT200_EVT1_GPP_OUT_VAL_MID;
pBoardInfo->gppPolarityValLow = GFLT200_EVT1_GPP_POL_LOW;
pBoardInfo->gppPolarityValMid = GFLT200_EVT1_GPP_POL_MID;
break;
default:
pr_err("GFLT200: unknown board version '%x'\n", board_ver);
/* fallthrough */
case GFLT200_EVT2_BOARD_VER:
pBoardInfo->numBoardMppConfigValue
= MV_ARRAY_SIZE(gflt200Evt2InfoBoardMppConfigValue);
pBoardInfo->pBoardMppConfigValue
= gflt200Evt2InfoBoardMppConfigValue;
pBoardInfo->numBoardGppInfo
= MV_ARRAY_SIZE(gflt200Evt2InfoBoardGppInfo),
pBoardInfo->pBoardGppInfo = gflt200Evt2InfoBoardGppInfo,
pBoardInfo->gppOutEnValLow = GFLT200_EVT2_GPP_OUT_ENA_LOW;
pBoardInfo->gppOutEnValMid = GFLT200_EVT2_GPP_OUT_ENA_MID;
pBoardInfo->gppOutValLow = GFLT200_EVT2_GPP_OUT_VAL_LOW;
pBoardInfo->gppOutValMid = GFLT200_EVT2_GPP_OUT_VAL_MID;
pBoardInfo->gppPolarityValLow = GFLT200_EVT2_GPP_POL_LOW;
pBoardInfo->gppPolarityValMid = GFLT200_EVT2_GPP_POL_MID;
break;
}
}
void __init mv_init_irq(void)
{
u32 gppMask,i;
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
coreId = whoAmI();
printk("IRQ initialize for core %d\n", coreId);
#endif
/* Disable all interrupts initially. */
if (0 == coreId)
{
MV_REG_WRITE(GPP_INT_MASK_REG(0), 0);
MV_REG_WRITE(GPP_INT_LVL_REG(0), 0);
}
MV_REG_WRITE(CPU_INT_MASK_LOW_REG(coreId), 0);
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), 0);
/* Set Gpp interrupts as needed */
if (0 == coreId) /*GPP for core 0 only*/
{
gppMask = mvBoardGpioIntMaskGet();
mvGppTypeSet(0, gppMask , (MV_GPP_IN & gppMask));
mvGppPolaritySet(0, gppMask , (MV_GPP_IN_INVERT & gppMask));
/* clear all int */
MV_REG_WRITE(GPP_INT_MASK_REG(0), 0);
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), IRQ_GPP_MASK);
}
else
MV_REG_WRITE(CPU_INT_MASK_HIGH_REG(coreId), 0);
/* Do the core module ones */
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &mv_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* TBD. Add support for error interrupts */
return;
}
//----------------------------------------------------------------------
// RTC
//----------------------------------------------------------------------
void BuffaloGpio_RtcIntSetup(void)
{
mvGppTypeSet(0, BIT(BIT_RTC) , BIT(BIT_RTC)); // disable output
mvGppPolaritySet(0, BIT(BIT_RTC) , 0);
MV_REG_WRITE(GPP_INT_LVL_REG(0), 0);
}
/*******************************************************************************
**
** mvOnuPonMacBurstEnableInit
** ____________________________________________________________________________
**
** DESCRIPTION: The function init Burst Enable MPP
**
** PARAMETERS: None
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS mvOnuPonMacBurstEnableInit(void)
{
MV_U32 gpioGroup, gpioMask;
MV_STATUS status = MV_OK;
if (MV_6601_DEV_ID == mvCtrlModelGet())
{
/* PHY control register - output status set */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_IO_EN, ONU_PHY_OUTPUT, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl enable - output\n\r");
return(MV_ERROR);
}
/* Set SW BEN control for MC tranciever */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_SW_HW_SELECT, 1, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy SW ctrl select\n\r");
return(MV_ERROR);
}
/* PHY control register - force disable */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_SW_FORCE, 0, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy SW ctrl not force\n\r");
return(MV_ERROR);
}
} else if (mvCtrlRevGet() == ONU_ASIC_REV_Z2) {
/* KW2 ASIC Rev Z2 */
/* =============== */
PON_GPIO_GET(BOARD_GPP_PON_XVR_TX, gpioGroup, gpioMask);
if (gpioMask == PON_GPIO_NOT_USED)
return MV_ERROR;
status = mvGppTypeSet(gpioGroup, gpioMask, ~gpioMask/* 0-output allow transsmit*/);
if (status == MV_OK)
status = mvGppValueSet(gpioGroup, gpioMask, ~gpioMask/*0-disable signal*/);
else
return(status);
if (status == MV_OK)
status = mvGppTypeSet(gpioGroup, gpioMask, gpioMask /* 0-input NOT allow transsmit*/);
} else if (mvCtrlRevGet() == ONU_ASIC_REV_A0) {
/* KW2 ASIC Rev A0 */
/* =============== */
/* PHY control register - output status set */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_BEN_IO_EN, ONU_PHY_OUTPUT, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl enable - output\n\r");
return(MV_ERROR);
}
/* PHY control register - force disable */
status = asicOntMiscRegWrite(mvAsicReg_PON_SERDES_PHY_CTRL_1_FORCE_BEN_IO_EN, 0, 0);
if (status != MV_OK) {
mvPonPrint(PON_PRINT_ERROR, PON_ISR_MODULE,
"ERROR: asicOntMiscRegWrite failed for PON phy ctrl not force\n\r");
return(MV_ERROR);
}
}
return(status);
}
