/* MX3 has one interrupt *per* gpio port */
static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
u32 irq_stat;
struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
irq_stat = __raw_readl(port->base + GPIO_ISR) &
__raw_readl(port->base + GPIO_IMR);
BUG_ON(!irq_stat);
mxc_gpio_irq_handler(port, irq_stat);
}
/* MX2 has one interrupt *for all* gpio ports */
static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
int i;
u32 irq_msk, irq_stat;
struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
/* walk through all interrupt status registers */
for (i = 0; i < gpio_table_size; i++) {
irq_msk = __raw_readl(port[i].base + GPIO_IMR);
if (!irq_msk)
continue;
irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
if (irq_stat)
mxc_gpio_irq_handler(&port[i], irq_stat);
}
}
static void mxc_gpio_mux_irq_handler(u32 irq, struct irq_desc *desc,
struct pt_regs *regs)
{
int i;
u32 isr_reg = 0, imr_reg = 0, imr_val;
u32 int_valid;
struct gpio_port *port;
for (i = 0; i < GPIO_PORT_NUM; i++) {
port = &gpio_port[i];
isr_reg = port->base + GPIO_ISR;
imr_reg = port->base + GPIO_IMR;
imr_val = __raw_readl(imr_reg);
int_valid = __raw_readl(isr_reg) & imr_val;
if (int_valid) {
set_irq_data(irq, (void *)port);
mxc_gpio_irq_handler(irq, desc, regs);
}
}
}
