static void __init qong_init_nand_mtd(void) { /* init CS */ __raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3))); __raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3))); __raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3))); mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); /* enable pin */ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO)); if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable")) gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); /* ready/busy pin */ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO)); if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy")) gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB)); /* write protect pin */ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO)); if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp")) gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B)); platform_device_register(&qong_nand_device); }
static inline void mxc_init_imx_uart(void) { mxc_iomux_mode(MX31_PIN_CTS1__CTS1); mxc_iomux_mode(MX31_PIN_RTS1__RTS1); mxc_iomux_mode(MX31_PIN_TXD1__TXD1); mxc_iomux_mode(MX31_PIN_RXD1__RXD1); mxc_register_device(&mxc_uart_device0, &uart_pdata); }
static void __init mxc_init_i2c(void) { i2c_register_board_info(1, mx31ads_i2c1_devices, ARRAY_SIZE(mx31ads_i2c1_devices)); mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); imx31_add_imx_i2c1(NULL); }
static void __init mxc_init_i2c(void) { #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 mx31ads_i2c1_devices[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); #endif i2c_register_board_info(1, mx31ads_i2c1_devices, ARRAY_SIZE(mx31ads_i2c1_devices)); mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); imx31_add_imx_i2c1(NULL); }
static int __init kzm_init_ext_uart(void) { u8 tmp; /* * GPIO 1-1: external UART interrupt line */ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)); gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int"); gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); /* * Unmask UART interrupt */ tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); tmp |= 0x2; __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); serial_platform_data[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); serial8250_resources[1].start = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); serial8250_resources[1].end = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); return platform_device_register(&serial_device); }
static void mx31moboard_poweroff(void) { struct clk *clk = clk_get_sys("imx2-wdt.0", NULL); if (!IS_ERR(clk)) clk_enable(clk); mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST); __raw_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); }
static int __init kzm_init_smsc9118(void) { /* * GPIO 1-2: SMSC9118 interrupt line */ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO)); gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int"); gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); return platform_device_register(&kzm_smsc9118_device); }
static int __init kzm_init_smsc9118(void) { /* * GPIO 1-2: SMSC9118 interrupt line */ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO)); gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int"); gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); kzm_smsc9118_resources[1].start = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); kzm_smsc9118_resources[1].end = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); return platform_device_register(&kzm_smsc9118_device); }
/* * allocs a single pin: * - reserves the pin so that it is not claimed by another driver * - setups the iomux according to the configuration */ int mxc_iomux_alloc_pin(unsigned int pin, const char *label) { unsigned pad = pin & IOMUX_PADNUM_MASK; if (pad >= (PIN_MAX + 1)) { printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", pad, label ? label : "?"); return -EINVAL; } if (test_and_set_bit(pad, mxc_pin_alloc_map)) { printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", pad, label ? label : "?"); return -EBUSY; } mxc_iomux_mode(pin); return 0; }
/* * Board specific initialization. */ static void __init mxc_board_init(void) { platform_add_devices(devices, ARRAY_SIZE(devices)); mxc_iomux_mode(MX31_PIN_CTS1__CTS1); mxc_iomux_mode(MX31_PIN_RTS1__RTS1); mxc_iomux_mode(MX31_PIN_TXD1__TXD1); mxc_iomux_mode(MX31_PIN_RXD1__RXD1); imx_init_uart(0, &uart_pdata); mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3); mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3); imx_init_uart(2, &uart_pdata); }
static void __init mx31ads_init_expio(void) { int i; printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n"); /* * Configure INT line as GPIO input */ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO)); /* disable the interrupt and clear the status */ __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); __raw_writew(0xFFFF, PBC_INTSTATUS_REG); for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { set_irq_chip(i, &expio_irq_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); }