// Write new value to register
// input:
// reg - register number
// value - new value
// output: nRF24L01 status
uint8_t nRF24_RWReg(uint8_t reg, uint8_t value) {
uint8_t status;
CSN_L();
status = nRF24_ReadWrite(reg); // Select register
nRF24_ReadWrite(value); // Write value to register
CSN_H();
return status;
}
// Send buffer to nRF24L01
// input:
// reg - register number
// pBuf - pointer to buffer
// count - bytes count
// output: nRF24L01 status
uint8_t nRF24_WriteBuf(uint8_t reg, uint8_t *pBuf, uint8_t count) {
uint8_t status,i;
CSN_L();
status = nRF24_ReadWrite(reg);
for (i = 0; i < count; i++) nRF24_ReadWrite(*pBuf++);
CSN_H();
return status;
}
// Read nRF24L01 register
// input:
// reg - register number
// output: register value
uint8_t nRF24_ReadReg(uint8_t reg) {
uint8_t value;
CSN_L();
nRF24_ReadWrite(reg);
value = nRF24_ReadWrite(0);
CSN_H();
return value;
}
// Get data from nRF24L01 into buffer
// input:
// reg - register number
// pBuf - pointer to buffer
// count - bytes count
// output: nRF24L01 status
uint8_t nRF24_ReadBuf(uint8_t reg, uint8_t *pBuf, uint8_t count) {
uint8_t status,i;
CSN_L();
status = nRF24_ReadWrite(reg);
for (i = 0; i < count; i++) pBuf[i] = nRF24_ReadWrite(0);
CSN_L();
return status;
}
uint8_t nRF24_RXPacket(uint8_t* pBuf, uint8_t RX_PAYLOAD) {
uint8_t status;
status = nRF24_ReadReg(nRF24_REG_STATUS); // Read status register
if (status & nRF24_MASK_RX_DR) {
if ((status & 0x0E) == 0) {
// pipe 0
nRF24_ReadBuf(nRF24_CMD_R_RX_PAYLOAD,pBuf,RX_PAYLOAD); // read received payload from RX FIFO buffer
}
nRF24_ReadWrite(nRF24_CMD_FLUSH_RX); // Flush RX FIFO buffer
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_STATUS,status | 0x70); // Clear RX_DR, TX_DS, MAX_RT flags
//return nRF24_MASK_RX_DR;
return status;
}
// Some banana happens
nRF24_ReadWrite(nRF24_CMD_FLUSH_RX); // Flush RX FIFO buffer
nRF24_RWReg(nRF24_CMD_WREG | nRF24_REG_STATUS,status | 0x70); // Clear RX_DR, TX_DS, MAX_RT flags
return status;
}
