/*! * This function is called during the driver binding process. * * @param pdev the device structure used to store device specific * information that is used by the suspend, resume and * remove functions * * @return The function always returns 0. */ int board_nand_init(struct nand_chip *nand) { struct mxs_nand_info *nand_info; int err; nand_info = malloc(sizeof(struct mxs_nand_info)); if (!nand_info) { printf("MXS NAND: Failed to allocate private data\n"); return -ENOMEM; } memset(nand_info, 0, sizeof(struct mxs_nand_info)); err = mxs_nand_alloc_buffers(nand_info); if (err) goto err1; err = mxs_nand_init(nand_info); if (err) goto err2; memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout)); nand_set_controller_data(nand, nand_info); nand->options |= NAND_NO_SUBPAGE_WRITE; nand->cmd_ctrl = mxs_nand_cmd_ctrl; nand->dev_ready = mxs_nand_device_ready; nand->select_chip = mxs_nand_select_chip; nand->block_bad = mxs_nand_block_bad; nand->scan_bbt = mxs_nand_scan_bbt; nand->read_byte = mxs_nand_read_byte; nand->read_buf = mxs_nand_read_buf; nand->write_buf = mxs_nand_write_buf; nand->ecc.read_page = mxs_nand_ecc_read_page; nand->ecc.write_page = mxs_nand_ecc_write_page; nand->ecc.read_oob = mxs_nand_ecc_read_oob; nand->ecc.write_oob = mxs_nand_ecc_write_oob; nand->ecc.layout = &fake_ecc_layout; nand->ecc.mode = NAND_ECC_HW; nand->ecc.bytes = 9; nand->ecc.size = 512; nand->ecc.strength = 8; return 0; err2: free(nand_info->data_buf); free(nand_info->cmd_buf); err1: free(nand_info); return err; }
/* * Initialize chip structure */ static int ndfc_chip_init(struct ndfc_controller *ndfc, struct device_node *node) { struct device_node *flash_np; struct nand_chip *chip = &ndfc->chip; struct mtd_info *mtd = nand_to_mtd(chip); int ret; chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA; chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA; chip->cmd_ctrl = ndfc_hwcontrol; chip->dev_ready = ndfc_ready; chip->select_chip = ndfc_select_chip; chip->chip_delay = 50; chip->controller = &ndfc->ndfc_control; chip->read_buf = ndfc_read_buf; chip->write_buf = ndfc_write_buf; chip->ecc.correct = nand_correct_data; chip->ecc.hwctl = ndfc_enable_hwecc; chip->ecc.calculate = ndfc_calculate_ecc; chip->ecc.mode = NAND_ECC_HW; chip->ecc.size = 256; chip->ecc.bytes = 3; chip->ecc.strength = 1; nand_set_controller_data(chip, ndfc); mtd->dev.parent = &ndfc->ofdev->dev; flash_np = of_get_next_child(node, NULL); if (!flash_np) return -ENODEV; nand_set_flash_node(chip, flash_np); mtd->name = kasprintf(GFP_KERNEL, "%s.%s", dev_name(&ndfc->ofdev->dev), flash_np->name); if (!mtd->name) { ret = -ENOMEM; goto err; } ret = nand_scan(mtd, 1); if (ret) goto err; ret = mtd_device_register(mtd, NULL, 0); err: of_node_put(flash_np); if (ret) kfree(mtd->name); return ret; }
int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) { if (fun->width != 8 && fun->width != 16 && fun->width != 32) return -ENOSYS; fun->last_ctrl = NAND_CLE; nand_set_controller_data(chip, fun); chip->chip_delay = fun->chip_delay; chip->ecc.mode = NAND_ECC_SOFT; chip->cmd_ctrl = fun_cmd_ctrl; #if CONFIG_SYS_NAND_MAX_CHIPS > 1 chip->select_chip = fun_select_chip; #endif chip->read_byte = upm_nand_read_byte; chip->read_buf = upm_nand_read_buf; chip->write_buf = upm_nand_write_buf; if (fun->dev_ready) chip->dev_ready = nand_dev_ready; return 0; }
static int bcm47xxnflash_probe(struct platform_device *pdev) { struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev); struct bcm47xxnflash *b47n; struct mtd_info *mtd; int err = 0; b47n = devm_kzalloc(&pdev->dev, sizeof(*b47n), GFP_KERNEL); if (!b47n) return -ENOMEM; nand_set_controller_data(&b47n->nand_chip, b47n); mtd = nand_to_mtd(&b47n->nand_chip); mtd->dev.parent = &pdev->dev; b47n->cc = container_of(nflash, struct bcma_drv_cc, nflash); if (b47n->cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { err = bcm47xxnflash_ops_bcm4706_init(b47n); } else { pr_err("Device not supported\n"); err = -ENOTSUPP; } if (err) { pr_err("Initialization failed: %d\n", err); return err; } platform_set_drvdata(pdev, b47n); err = mtd_device_parse_register(mtd, probes, NULL, NULL, 0); if (err) { pr_err("Failed to register MTD device: %d\n", err); return err; } return 0; }
static int __init txx9ndfmc_probe(struct platform_device *dev) { struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); int hold, spw; int i; struct txx9ndfmc_drvdata *drvdata; unsigned long gbusclk = plat->gbus_clock; struct resource *res; drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; res = platform_get_resource(dev, IORESOURCE_MEM, 0); drvdata->base = devm_ioremap_resource(&dev->dev, res); if (IS_ERR(drvdata->base)) return PTR_ERR(drvdata->base); hold = plat->hold ?: 20; /* tDH */ spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */ hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold); spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw); if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD) hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */ spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */ hold = clamp(hold, 1, 15); drvdata->hold = hold; spw = clamp(spw, 1, 15); drvdata->spw = spw; dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n", (gbusclk + 500000) / 1000000, hold, spw); nand_controller_init(&drvdata->controller); drvdata->controller.ops = &txx9ndfmc_controller_ops; platform_set_drvdata(dev, drvdata); txx9ndfmc_initialize(dev); for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) { struct txx9ndfmc_priv *txx9_priv; struct nand_chip *chip; struct mtd_info *mtd; if (!(plat->ch_mask & (1 << i))) continue; txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv), GFP_KERNEL); if (!txx9_priv) continue; chip = &txx9_priv->chip; mtd = nand_to_mtd(chip); mtd->dev.parent = &dev->dev; chip->read_byte = txx9ndfmc_read_byte; chip->read_buf = txx9ndfmc_read_buf; chip->write_buf = txx9ndfmc_write_buf; chip->cmd_ctrl = txx9ndfmc_cmd_ctrl; chip->dev_ready = txx9ndfmc_dev_ready; chip->ecc.calculate = txx9ndfmc_calculate_ecc; chip->ecc.correct = txx9ndfmc_correct_data; chip->ecc.hwctl = txx9ndfmc_enable_hwecc; chip->ecc.mode = NAND_ECC_HW; chip->ecc.strength = 1; chip->chip_delay = 100; chip->controller = &drvdata->controller; nand_set_controller_data(chip, txx9_priv); txx9_priv->dev = dev; if (plat->ch_mask != 1) { txx9_priv->cs = i; txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u", dev_name(&dev->dev), i); } else { txx9_priv->cs = -1; txx9_priv->mtdname = kstrdup(dev_name(&dev->dev), GFP_KERNEL); } if (!txx9_priv->mtdname) { kfree(txx9_priv); dev_err(&dev->dev, "Unable to allocate MTD name.\n"); continue; } if (plat->wide_mask & (1 << i)) chip->options |= NAND_BUSWIDTH_16; if (nand_scan(mtd, 1)) { kfree(txx9_priv->mtdname); kfree(txx9_priv); continue; } mtd->name = txx9_priv->mtdname; mtd_device_register(mtd, NULL, 0); drvdata->mtds[i] = mtd; } return 0; }
/* * Probe for the NAND device. */ static int oxnas_nand_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct device_node *nand_np; struct oxnas_nand_ctrl *oxnas; struct nand_chip *chip; struct mtd_info *mtd; struct resource *res; int nchips = 0; int count = 0; int err = 0; /* Allocate memory for the device structure (and zero it) */ oxnas = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip), GFP_KERNEL); if (!oxnas) return -ENOMEM; nand_hw_control_init(&oxnas->base); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); oxnas->io_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(oxnas->io_base)) return PTR_ERR(oxnas->io_base); oxnas->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(oxnas->clk)) oxnas->clk = NULL; /* Only a single chip node is supported */ count = of_get_child_count(np); if (count > 1) return -EINVAL; clk_prepare_enable(oxnas->clk); device_reset_optional(&pdev->dev); for_each_child_of_node(np, nand_np) { chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip), GFP_KERNEL); if (!chip) return -ENOMEM; chip->controller = &oxnas->base; nand_set_flash_node(chip, nand_np); nand_set_controller_data(chip, oxnas); mtd = nand_to_mtd(chip); mtd->dev.parent = &pdev->dev; mtd->priv = chip; chip->cmd_ctrl = oxnas_nand_cmd_ctrl; chip->read_buf = oxnas_nand_read_buf; chip->read_byte = oxnas_nand_read_byte; chip->write_buf = oxnas_nand_write_buf; chip->chip_delay = 30; /* Scan to find existence of the device */ err = nand_scan(mtd, 1); if (err) return err; err = mtd_device_register(mtd, NULL, 0); if (err) { nand_release(mtd); return err; } oxnas->chips[nchips] = chip; ++nchips; }
/* * Main initialization routine */ static int ams_delta_init(struct platform_device *pdev) { struct nand_chip *this; struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); void __iomem *io_base; int err = 0; if (!res) return -ENXIO; /* Allocate memory for MTD device structure and private data */ this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL); if (!this) { printk (KERN_WARNING "Unable to allocate E3 NAND MTD device structure.\n"); err = -ENOMEM; goto out; } ams_delta_mtd = nand_to_mtd(this); ams_delta_mtd->owner = THIS_MODULE; /* * Don't try to request the memory region from here, * it should have been already requested from the * gpio-omap driver and requesting it again would fail. */ io_base = ioremap(res->start, resource_size(res)); if (io_base == NULL) { dev_err(&pdev->dev, "ioremap failed\n"); err = -EIO; goto out_free; } nand_set_controller_data(this, (void *)io_base); /* Set address of NAND IO lines */ this->IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH; this->IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT; this->read_byte = ams_delta_read_byte; this->write_buf = ams_delta_write_buf; this->read_buf = ams_delta_read_buf; this->cmd_ctrl = ams_delta_hwcontrol; if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) { this->dev_ready = ams_delta_nand_ready; } else { this->dev_ready = NULL; printk(KERN_NOTICE "Couldn't request gpio for Delta NAND ready.\n"); } /* 25 us command delay time */ this->chip_delay = 30; this->ecc.mode = NAND_ECC_SOFT; this->ecc.algo = NAND_ECC_HAMMING; platform_set_drvdata(pdev, io_base); /* Set chip enabled, but */ err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio)); if (err) goto out_gpio; /* Scan to find existence of the device */ err = nand_scan(ams_delta_mtd, 1); if (err) goto out_mtd; /* Register the partitions */ mtd_device_register(ams_delta_mtd, partition_info, ARRAY_SIZE(partition_info)); goto out; out_mtd: gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio)); out_gpio: gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB); iounmap(io_base); out_free: kfree(this); out: return err; }
/* * spinand_probe - [spinand Interface] * @spi_nand: registered device driver. * * Description: * To set up the device driver parameters to make the device available. */ static int spinand_probe(struct spi_device *spi_nand) { struct mtd_info *mtd; struct nand_chip *chip; struct spinand_info *info; struct spinand_state *state; info = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info), GFP_KERNEL); if (!info) return -ENOMEM; info->spi = spi_nand; spinand_lock_block(spi_nand, BL_ALL_UNLOCKED); state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state), GFP_KERNEL); if (!state) return -ENOMEM; info->priv = state; state->buf_ptr = 0; state->buf = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL); if (!state->buf) return -ENOMEM; chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip), GFP_KERNEL); if (!chip) return -ENOMEM; #ifdef CONFIG_MTD_SPINAND_ONDIEECC chip->ecc.mode = NAND_ECC_HW; chip->ecc.size = 0x200; chip->ecc.bytes = 0x6; chip->ecc.steps = 0x4; chip->ecc.strength = 1; chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; chip->ecc.layout = &spinand_oob_64; chip->ecc.read_page = spinand_read_page_hwecc; chip->ecc.write_page = spinand_write_page_hwecc; #else chip->ecc.mode = NAND_ECC_SOFT; if (spinand_disable_ecc(spi_nand) < 0) pr_info("%s: disable ecc failed!\n", __func__); #endif nand_set_flash_node(chip, spi_nand->dev.of_node); nand_set_controller_data(chip, info); chip->read_buf = spinand_read_buf; chip->write_buf = spinand_write_buf; chip->read_byte = spinand_read_byte; chip->cmdfunc = spinand_cmdfunc; chip->waitfunc = spinand_wait; chip->options |= NAND_CACHEPRG; chip->select_chip = spinand_select_chip; mtd = nand_to_mtd(chip); dev_set_drvdata(&spi_nand->dev, mtd); mtd->dev.parent = &spi_nand->dev; mtd->oobsize = 64; if (nand_scan(mtd, 1)) return -ENXIO; return mtd_device_register(mtd, NULL, 0); }
/* * Probe for the NAND device. */ static int xway_nand_probe(struct platform_device *pdev) { struct xway_nand_data *data; struct mtd_info *mtd; struct resource *res; int err; u32 cs; u32 cs_flag = 0; /* Allocate memory for the device structure (and zero it) */ data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), GFP_KERNEL); if (!data) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); data->nandaddr = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(data->nandaddr)) return PTR_ERR(data->nandaddr); nand_set_flash_node(&data->chip, pdev->dev.of_node); mtd = nand_to_mtd(&data->chip); mtd->dev.parent = &pdev->dev; data->chip.cmd_ctrl = xway_cmd_ctrl; data->chip.dev_ready = xway_dev_ready; data->chip.select_chip = xway_select_chip; data->chip.write_buf = xway_write_buf; data->chip.read_buf = xway_read_buf; data->chip.read_byte = xway_read_byte; data->chip.chip_delay = 30; data->chip.ecc.mode = NAND_ECC_SOFT; data->chip.ecc.algo = NAND_ECC_HAMMING; platform_set_drvdata(pdev, data); nand_set_controller_data(&data->chip, data); /* load our CS from the DT. Either we find a valid 1 or default to 0 */ err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs); if (!err && cs == 1) cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; /* setup the EBU to run in NAND mode on our base addr */ ltq_ebu_w32(CPHYSADDR(data->nandaddr) | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P | cs_flag, EBU_NAND_CON); /* Scan to find existence of the device */ err = nand_scan(mtd, 1); if (err) return err; err = mtd_device_register(mtd, NULL, 0); if (err) nand_release(mtd); return err; }