예제 #1
0
/*
 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 * - we have a stack and a place to store GD, both in SRAM
 * - no variable global data is available
 */
void board_init_f(ulong dummy)
{
	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	ccgr_init();
	gpr_init();

	/* setup GP timer */
	timer_init();

#ifdef CONFIG_BOARD_POSTCLK_INIT
	board_postclk_init();
#endif
#ifdef CONFIG_FSL_ESDHC
	get_clocks();
#endif

	/* Setup IOMUX and configure basics. */
	novena_spl_setup_iomux_audio();
	novena_spl_setup_iomux_buttons();
	novena_spl_setup_iomux_enet();
	novena_spl_setup_iomux_fpga();
	novena_spl_setup_iomux_i2c();
	novena_spl_setup_iomux_pcie();
	novena_spl_setup_iomux_sdhc();
	novena_spl_setup_iomux_spi();
	novena_spl_setup_iomux_uart();
	novena_spl_setup_iomux_video();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* Start the DDR DRAM */
	novena_read_spd(&novena_ddr_info, &novena_ddr3_cfg);
	mx6dq_dram_iocfg(novena_ddr3_cfg.width,
			 &novena_ddr_ioregs, &novena_grp_ioregs);
	mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &novena_ddr3_cfg);
	do_write_level_calibration();
	do_dqs_calibration();
	printf("Running post-config memory test... ");
	if (novena_memory_test())
		printf("Fail!\n");
	else
		printf("Pass\n");

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}
예제 #2
0
/*
 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 * - we have a stack and a place to store GD, both in SRAM
 * - no variable global data is available
 */
void board_init_f(ulong dummy)
{
	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	ccgr_init();
	gpr_init();

	/* setup GP timer */
	timer_init();

#ifdef CONFIG_BOARD_POSTCLK_INIT
	board_postclk_init();
#endif
#ifdef CONFIG_FSL_ESDHC
	get_clocks();
#endif

	/* Setup IOMUX and configure basics. */
	novena_spl_setup_iomux_audio();
	novena_spl_setup_iomux_buttons();
	novena_spl_setup_iomux_enet();
	novena_spl_setup_iomux_fpga();
	novena_spl_setup_iomux_i2c();
	novena_spl_setup_iomux_pcie();
	novena_spl_setup_iomux_sdhc();
	novena_spl_setup_iomux_spi();
	novena_spl_setup_iomux_uart();
	novena_spl_setup_iomux_video();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* Start the DDR DRAM */
	mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
	mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);

	/* Perform DDR DRAM calibration */
	udelay(100);
	mmdc_do_write_level_calibration();
	mmdc_do_dqs_calibration();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}