/* Write to a single register of nrf24 */
void nrf24_writeRegister(uint8_t reg, uint8_t* value, uint8_t len)
{
nrf24_csn_digitalWrite(LOW);
spi_transfer(W_REGISTER | (REGISTER_MASK & reg));
nrf24_transmitSync(value,len);
nrf24_csn_digitalWrite(HIGH);
}
/* Clocks only one byte into the given nrf24 register */
void nrf24_configRegister(uint8_t reg, uint8_t value)
{
nrf24_csn_digitalWrite(LOW);
spi_transfer(W_REGISTER | (REGISTER_MASK & reg));
spi_transfer(value);
nrf24_csn_digitalWrite(HIGH);
}
uint8_t nrf24_transmit(
uint32_t address,
uint8_t* packet,
uint16_t packetLen )
{
if (context.isTxMode == 0) return NRF24ERR_INVALID_MODE;
// check the parameters
if (packet == 0) return NRF24ERR_INVALID_INPUT_POINTER;
if (packetLen != context.payloadLength) return NRF24ERR_INVALID_PACKET_LENGTH;
// change the TX and RX address (pipe 0)
spi_writeRegister(RX_ADDR_P0, (uint8_t*)&address, sizeof(uint32_t));
spi_writeRegister(TX_ADDR, (uint8_t*)&address, sizeof(uint32_t));
// write the packet to the TX FIFO pading with zero (if necessary)
nrf24_csn_digitalWrite(LOW);
spi_transfer(W_TX_PAYLOAD);
spi_transmitSync(packet, packetLen);
nrf24_csn_digitalWrite(HIGH);
// wait for 10us to ensure the at least one packet will be sent if
// the 'stopTransmission' function is called immidiately
//usleep(10);
return NRF24_OK;
}
void nrf24_activate_special()
{
nrf24_csn_digitalWrite(LOW);
spi_transfer(ACTIVATE);
spi_transfer(0x73);
nrf24_csn_digitalWrite(HIGH);
}
/* Clocks only one byte into the given nrf24 register */
void nrf24_configRegister(uint8_t reg, uint8_t value)
{
nrf24_csn_digitalWrite(LOW);
spi_transfer(NRF24L01P_CMD_W_REGISTER | (NRF24L01P_CMD_REGISTER_MASK & reg), 0);
spi_transfer(value, 1);
nrf24_csn_digitalWrite(HIGH);
}
uint8_t nrf24_waitTransmission()
{
uint8_t status, result = 0xFF;
uint32_t sentAt = 0;
if (context.isTxMode == 0) return NRF24ERR_INVALID_MODE;
// This function will block until get TX_DS (transmission completed and ack'd)
// or MAX_RT (maximum retries, transmission failed). Additionaly, have a timeout
// (60ms) in case the radio don't set any flag.
sentAt = 0;//clock();
do
{
// read the current status
nrf24_csn_digitalWrite(LOW);
status = spi_transfer(NOP);
nrf24_csn_digitalWrite(HIGH);
// check if sending successful (TX_DS)
if ( status & (1 << TX_DS) )
result = NRF24_OK;
else
// check if max retries exceded (MAX_RT)
if ( status & (1 << MAX_RT) )
result = NRF24ERR_MAX_RETRANSMISSIONS;
else
// check if the timeout is reached
if ( /*clock()*/0 - sentAt < 60000)
result = NRF24ERR_TIMEOUT;
} while(result != 0xFF);
// clear the RX_DR, TX_DS and MAX_RT flags
spi_setRegister(STATUS, (1 << RX_DR) | (1 << TX_DS) | (1 << MAX_RT));
return result;
}
/* Read single register from nrf24 */
void nrf24_readRegister(uint8_t reg, uint8_t* value, uint8_t len)
{
nrf24_csn_digitalWrite(LOW);
spi_transfer(R_REGISTER | (REGISTER_MASK & reg), 0);
nrf24_transferSync(value,value,len);
nrf24_csn_digitalWrite(HIGH);
}
// Sends a data package to the default address. Be sure to send the correct
// amount of bytes as configured as payload on the receiver.
void nrf24_send(uint8_t* value)
{
/* Go to Standby-I first */
nrf24_ce_digitalWrite(LOW);
/* Set to transmitter mode , Power up if needed */
nrf24_powerUpTx();
/* Do we really need to flush TX fifo each time ? */
#if 1
/* Pull down chip select */
nrf24_csn_digitalWrite(LOW);
/* Write cmd to flush transmit FIFO */
spi_transfer(FLUSH_TX);
/* Pull up chip select */
nrf24_csn_digitalWrite(HIGH);
#endif
/* Pull down chip select */
nrf24_csn_digitalWrite(LOW);
/* Write cmd to write payload */
spi_transfer(W_TX_PAYLOAD);
/* Write payload */
nrf24_transmitSync(value,payload_len);
/* Pull up chip select */
nrf24_csn_digitalWrite(HIGH);
/* Start the transmission */
nrf24_ce_digitalWrite(HIGH);
}
uint8_t nrf24_getStatus()
{
uint8_t rv;
nrf24_csn_digitalWrite(LOW);
rv = spi_transfer(NRF24L01P_CMD_NOP, 1);
nrf24_csn_digitalWrite(HIGH);
return rv;
}
uint8_t nrf24_getStatus()
{
uint8_t rv;
nrf24_csn_digitalWrite(LOW);
rv = spi_transfer(NOP);
nrf24_csn_digitalWrite(HIGH);
return rv;
}
/* Returns the length of data waiting in the RX fifo */
uint8_t nrf24_payloadLength()
{
uint8_t status;
nrf24_csn_digitalWrite(LOW);
spi_transfer(NRF24L01P_CMD_R_RX_PL_WID, 0);
status = spi_transfer(0x00, 1);
nrf24_csn_digitalWrite(HIGH);
return status;
}
/* Returns the length of data waiting in the RX fifo */
uint8_t nrf24_payloadLength()
{
uint8_t status;
nrf24_csn_digitalWrite(LOW);
spi_transfer(R_RX_PL_WID);
status = spi_transfer(0x00);
nrf24_csn_digitalWrite(HIGH);
return status;
}
void nrf24_powerUpRx()
{
nrf24_csn_digitalWrite(LOW);
spi_transfer(FLUSH_RX);
nrf24_csn_digitalWrite(HIGH);
nrf24_configRegister(STATUS,(1<<RX_DR)|(1<<TX_DS)|(1<<MAX_RT));
nrf24_ce_digitalWrite(LOW);
nrf24_configRegister(CONFIG,nrf24_CONFIG|((1<<PWR_UP)|(1<<PRIM_RX)));
nrf24_ce_digitalWrite(HIGH);
}
void nrf24_powerUpRx()
{
nrf24_csn_digitalWrite(LOW);
spi_transfer(NRF24L01P_CMD_FLUSH_RX, 1);
nrf24_csn_digitalWrite(HIGH);
nrf24_configRegister(NRF24L01P_REG_STATUS,(1<<NRF24L01P_SHIFT_RX_DR)|(1<<NRF24L01P_SHIFT_TX_DS)|(1<<NRF24L01P_SHIFT_MAX_RT));
nrf24_ce_digitalWrite(LOW);
nrf24_configRegister(NRF24L01P_REG_CONFIG,NRF_INIT|((1<<NRF24L01P_SHIFT_PWR_UP)|(1<<NRF24L01P_SHIFT_PRIM_RX)));
nrf24_ce_digitalWrite(HIGH);
}
uint8_t spi_getRegister(
uint8_t reg,
uint8_t *value )
{
uint8_t temp;
nrf24_csn_digitalWrite(LOW);
spi_transfer(R_REGISTER | (REGISTER_MASK & reg));
spi_transferSync(&temp, &temp, 1);
nrf24_csn_digitalWrite(HIGH);
if (value != 0) *value = temp;
return temp;
}
bool nrf24_isTransmitting()
{
uint8_t status;
if (context.isTxMode == 0) return FALSE;
// read the current status
nrf24_csn_digitalWrite(LOW);
status = spi_transfer(NOP);
nrf24_csn_digitalWrite(HIGH);
// if sending successful (TX_DS) or max retries exceded (MAX_RT)
if((status & ((1 << TX_DS) | (1 << MAX_RT))))
return FALSE;
return TRUE;
}
/* Reads payload bytes into data array */
void nrf24_getData(uint8_t* data)
{
/* Pull down chip select */
nrf24_csn_digitalWrite(LOW);
/* Send cmd to read rx payload */
spi_transfer( R_RX_PAYLOAD );
/* Read payload */
nrf24_transferSync(data,data,payload_len);
/* Pull up chip select */
nrf24_csn_digitalWrite(HIGH);
/* Reset status register */
nrf24_configRegister(STATUS,(1<<RX_DR));
}
uint8_t nrf24_initialize()
{
nrf24_setupPins();
nrf24_ce_digitalWrite(LOW);
nrf24_csn_digitalWrite(HIGH);
nrf24_config(0, 32);
return NRF24_OK;
}
uint8_t nrf24_startTransmission()
{
if (context.isRxMode != 0) return NRF24ERR_INVALID_MODE;
if (context.isTxMode != 0) return NRF24_OK;
// flush the RX queue
nrf24_csn_digitalWrite(LOW);
spi_transfer(FLUSH_RX);
nrf24_csn_digitalWrite(HIGH);
// clear the RX_DR, TX_DS and MAX_RT flags
spi_setRegister(STATUS,(1<<RX_DR)|(1<<TX_DS)|(1<<MAX_RT));
// power up the radio in TX mode (or standby-II if TX FIFO is empty)
nrf24_ce_digitalWrite(LOW);
spi_setRegister(CONFIG, (1 << PWR_UP) | (0 << PRIM_RX) );
nrf24_ce_digitalWrite(HIGH);
context.isTxMode = TRUE;
printf("Radio is ready to transmit\n");
return NRF24_OK;
}
uint8_t nrf24_startListening()
{
if (context.isTxMode != 0) return NRF24ERR_INVALID_MODE;
if (context.isRxMode != 0) return NRF24_OK;
// flush the RX queue
nrf24_csn_digitalWrite(LOW);
spi_transfer(FLUSH_RX);
nrf24_csn_digitalWrite(HIGH);
// clear the RX_DR, TX_DS and MAX_RT flags
spi_setRegister(STATUS,(1<<RX_DR)|(1<<TX_DS)|(1<<MAX_RT));
// power up the radio in RX mode
nrf24_ce_digitalWrite(LOW);
spi_setRegister(CONFIG, (1 << PWR_UP) | (1 << PRIM_RX) );
nrf24_ce_digitalWrite(HIGH);
context.isRxMode = TRUE;
printf("Radio is listening\n");
return NRF24_OK;
}
void nrf24_test_sender()
{
int temp;
data_array[0] = 0x00;
data_array[1] = 0xAA;
data_array[2] = 0x55;
data_array[3] = 0x00;
nrf24_ce_digitalWrite(LOW);
/* Set to transmitter mode , Power up if needed */
nrf24_powerUpTx();
/* Do we really need to flush TX fifo each time ? */
#if 1
/* Pull down chip select */
nrf24_csn_digitalWrite(LOW);
/* Write cmd to flush transmit FIFO */
spi_transfer(FLUSH_TX);
/* Pull up chip select */
nrf24_csn_digitalWrite(HIGH);
#endif
/* Pull down chip select */
nrf24_csn_digitalWrite(LOW);
/* Write cmd to write payload */
spi_transfer(W_TX_PAYLOAD);
/* Write payload */
nrf24_transmitSync(data_array, 30);
/* Pull up chip select */
nrf24_csn_digitalWrite(HIGH);
/* Start the transmission */
nrf24_ce_digitalWrite(HIGH);
/* Wait for transmission to end */
}
/* init the hardware pins */
void nrf24_init()
{
// nrf24_setupPins();
nrf24_ce_digitalWrite(LOW);
nrf24_csn_digitalWrite(HIGH);
DDRB |= (1<<PINB0);
DDRD |= (1<<PIND7);
PORTB &= ~(1<<PINB0);
PORTD |= (1<<PIND7);
}
uint8_t nrf24_receive(
uint8_t* data )
{
if (context.isRxMode == 0) return NRF24ERR_INVALID_MODE;
// TODO: check whether the RX FIFO is empty
// Pull down chip select
nrf24_csn_digitalWrite(LOW);
// Send cmd to read rx payload
spi_transfer( R_RX_PAYLOAD );
// Read payload
spi_transferSync(data,data,context.payloadLength);
// Pull up chip select
nrf24_csn_digitalWrite(HIGH);
// Reset status register
spi_setRegister(STATUS,(1<<RX_DR));
return NRF24_OK;
}
/* init the hardware pins */
void nrf24_init()
{
nrf24_setupPins();
nrf24_ce_digitalWrite(LOW);
nrf24_csn_digitalWrite(HIGH);
#if defined (__AVR_ATmega328P__)
/* Set SS pin output */
DDRB |= (1<<2);
/* Set SPI peripheral @Fosc/2 */
SPCR = (1<<SPE)|(1<<MSTR);
SPSR |= (1<<SPI2X);
#endif
}
/* init the hardware pins */
void nrf24_init()
{
nrf24_setupPins();
nrf24_ce_digitalWrite(LOW);
nrf24_csn_digitalWrite(HIGH);
nrf24_ce_digitalWrite(HIGH);
nrf24_config(2,32);
//nrf24_readRegister(CONFIG,&tx1,1);
//tx1=0;
//nrf24_configRegister(RF_CH,2);
//nrf24_readRegister(EN_AA,&tx1,1);
//tx1=0;
nrf24_configRegister(RF_CH,2);
nrf24_readRegister(RF_CH,&tx1,1);
tx1=0;
nrf24_readRegister(CONFIG,&tx1,1);
tx1=0;
nrf24_readRegister(RX_ADDR_P0,&readData,5);
tx1=0;
nrf24_readRegister(RF_SETUP,&tx1,1);
tx1=0;
nrf24_readRegister(TX_ADDR,&readData,5);
tx1=0;
nrf24_configRegister(SETUP_AW,2);
//nrf24_readRegister(SETUP_AW,&tx1,1);
//nrf24_configRegister(DYNPD,0x00);
//nrf24_configRegister(FEATURE,0x00);
//nrf24_tx_address(&tx_address11);
//copy_paste();
// nrf_cmd(0x20, 0x12); //on, no crc, int on RX/TX done
// nrf_cmd(0x21, 0x00); //no auto-acknowledge
// nrf_cmd(0x22, 0x00); //no RX
// nrf_cmd(0x23, 0x02); //5-byte address
// nrf_cmd(0x24, 0x00); //no auto-retransmit
// nrf_cmd(0x26, 0x06); //1MBps at 0dBm
// nrf_cmd(0x27, 0x3E); //clear various flags
// nrf_cmd(0x3C, 0x00); //no dynamic payloads
// nrf_cmd(0x3D, 0x00); //no features
// nrf_cmd(0x31, 32); //always RX 32 bytes
// nrf_cmd(0x22, 0x01); //RX on pipe 0
}
/* init the hardware pins */
void nrf24_init()
{
nrf24_ce_digitalWrite(LOW);
nrf24_csn_digitalWrite(HIGH);
}
/* init the hardware pins */
void nrf24_init()
{
//SPIM_Funk_Start();
nrf24_ce_digitalWrite(LOW);
nrf24_csn_digitalWrite(HIGH);
}
void nrf24_send(const void *value, unsigned short payload_len)
{
//This is supposed to be modularisd and call prepare and transmit but for now we just do
//everythung here
/* Go to Standby-I first */
int i=0;
length_arr=payload_len;
//payload_len=23;
//nrf24_test_sender();
//return;
for(i=0;i<127;i++)
{
data[i]=0;
}
for(i=0;i<payload_len;i++)
{
data[i]=((uint8_t *)value)[i];
}
nrf24_ce_digitalWrite(LOW);
/* Set to transmitter mode , Power up if needed */
nrf24_powerUpTx();
/* Do we really need to flush TX fifo each time ? */
#if 1
/* Pull down chip select */
nrf24_csn_digitalWrite(LOW);
/* Write cmd to flush transmit FIFO */
spi_transfer(FLUSH_TX);
/* Pull up chip select */
nrf24_csn_digitalWrite(HIGH);
#endif
/* Pull down chip select */
nrf24_csn_digitalWrite(LOW);
/* Write cmd to write payload */
spi_transfer(W_TX_PAYLOAD);
/* Write payload */
nrf24_transmitSync(value,payload_len);
/* Pull up chip select */
nrf24_csn_digitalWrite(HIGH);
/* Start the transmission */
nrf24_ce_digitalWrite(HIGH);
//while(true);
//while(1);
//while(1);
while(nrf24_isSending());
//nrf24_powerUpRx();
}