/** * @brief Detaches an interrupt handler from the CAN peripheral * * Detaches an interrupt handler from the CAN peripheral. */ void can_detach_interrupt(can_dev* const dev, can_interrupt_type interrupt_type) { switch (interrupt_type) { case CAN_INT_TX: dev->tx_handler = NULL; nvic_irq_disable(dev->tx_irq_num); break; case CAN_INT_RX: dev->rx_handler = NULL; nvic_irq_disable(dev->rx_irq_num); break; case CAN_INT_SC: dev->sc_handler = NULL; nvic_irq_disable(dev->sc_irq_num); break; default: return; } }
void usart_release(usart_num num) { const usart_dev *dev = usart_get_dev(num); rcc_reset_dev(dev->clk_id); nvic_irq_disable(dev->irq); usart_set_unused(num); }
void SPI1_IRQHandler(void) { static rt_uint8_t is_cmd; static rt_uint8_t cmd; rt_interrupt_enter(); if(spi_is_rx_nonempty(spi1.c_dev())) { nvic_irq_disable(NVIC_SPI1); if(!is_cmd) { cmd = spi1.read(); } is_cmd = !is_cmd; wrtnode2r_spi_bridge_rx_isr(cmd, is_cmd); nvic_irq_enable(NVIC_SPI1); } rt_interrupt_leave(); }
/** * @brief Detach a DMA transfer interrupt handler. * * After calling this function, the given channel's interrupts will be * disabled. * * @param dev DMA device * @param stream Stream whose handler to detach * @sideeffect Clears interrupt enable bits in the channel's CCR register. * @see dma_attach_interrupt() */ void dma_detach_interrupt(dma_dev *dev, dma_stream stream) { nvic_irq_disable(dev->handlers[stream].irq_line); dev->handlers[stream].handler = NULL; }
void usb_midi_disable(gpio_dev *disc_dev, uint8 disc_bit) { /* Turn off the interrupt and signal disconnect (see e.g. USB 2.0 * spec, section 7.1.7.3). */ nvic_irq_disable(NVIC_USB_LP_CAN_RX0); gpio_write_bit(disc_dev, disc_bit, 1); }
rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) { const struct pin_index *index; const struct pin_irq_map *irqmap; rt_base_t level; rt_int32_t hdr_index = -1; exti_trig_type_enum trigger_mode; index = get_pin(pin); if (index == RT_NULL) { return RT_EINVAL; } if (enabled == PIN_IRQ_ENABLE) { hdr_index = bit2bitno(index->pin); if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) { return RT_EINVAL; } level = rt_hw_interrupt_disable(); if (pin_irq_hdr_tab[hdr_index].pin == -1) { rt_hw_interrupt_enable(level); return RT_EINVAL; } irqmap = &pin_irq_map[hdr_index]; switch (pin_irq_hdr_tab[hdr_index].mode) { case PIN_IRQ_MODE_RISING: trigger_mode = EXTI_TRIG_RISING; break; case PIN_IRQ_MODE_FALLING: trigger_mode = EXTI_TRIG_FALLING; break; case PIN_IRQ_MODE_RISING_FALLING: trigger_mode = EXTI_TRIG_BOTH; break; default: rt_hw_interrupt_enable(level); return RT_EINVAL; } //rcu_periph_clock_enable(RCU_AF); /* enable and set interrupt priority */ nvic_irq_enable(irqmap->irqno, 5U); /* connect EXTI line to GPIO pin */ syscfg_exti_line_config(index->port_src, index->pin_src); /* configure EXTI line */ exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); exti_interrupt_flag_clear((exti_line_enum)(index->pin)); rt_hw_interrupt_enable(level); } else if (enabled == PIN_IRQ_DISABLE) { irqmap = get_pin_irq_map(index->pin); if (irqmap == RT_NULL) { return RT_EINVAL; } nvic_irq_disable(irqmap->irqno); } else { return RT_EINVAL; } return RT_EOK; }